From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>, qemu-devel@nongnu.org
Cc: Jason Wang <jasowang@redhat.com>,
Laurent Vivier <laurent@vivier.eu>,
Finn Thain <fthain@linux-m68k.org>
Subject: Re: [RFC PATCH 3/6] dp8393x: Restrict bus access to 16/32-bit operations
Date: Sat, 3 Jul 2021 15:52:49 +0100 [thread overview]
Message-ID: <6bbd0c5b-bbc5-7d2f-75e6-d2538631def3@ilande.co.uk> (raw)
In-Reply-To: <20210703141947.352295-4-f4bug@amsat.org>
On 03/07/2021 15:19, Philippe Mathieu-Daudé wrote:
> Per the DP83932C datasheet from July 1995:
>
> 1. Functional Description
> 1.3 DATA WIDTH AND BYTE ORDERING
>
> The SONIC can be programmed to operate with
> either 32-bit or 16-bit wide memory.
>
> Restrict the memory bus to reject 8/64-bit accesses.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/net/dp8393x.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
> index d16ade2b198..c9b478c127c 100644
> --- a/hw/net/dp8393x.c
> +++ b/hw/net/dp8393x.c
> @@ -695,6 +695,8 @@ static const MemoryRegionOps dp8393x_ops = {
> .write = dp8393x_write,
> .impl.min_access_size = 2,
> .impl.max_access_size = 2,
> + .valid.min_access_size = 2,
> + .valid.max_access_size = 4,
> .endianness = DEVICE_NATIVE_ENDIAN,
> };
The changes to .valid are correct, but I don't think the above reference to the
datasheet is. My reading of the sentence in section 1.3 "The SONIC can be programmed
to operate with either 32-bit or 16-bit wide memory" (along with subsequent
references to the DW bit in the DCR) is that this section is describing bus master
transfers as per figure 1-5 instead of register accesses which is what this patch
changes.
I think you could simply squash this patch into the previous one since there will
already be a behaviour change there.
ATB,
Mark.
next prev parent reply other threads:[~2021-07-03 14:53 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-03 14:19 [RFC PATCH 0/6] dp8393x: Housekeeping Philippe Mathieu-Daudé
2021-07-03 14:19 ` [PATCH 1/6] dp8393x: fix CAM descriptor entry index Philippe Mathieu-Daudé
2021-07-03 14:19 ` [PATCH 2/6] dp8393x: don't force 32-bit register access Philippe Mathieu-Daudé
2021-07-03 14:39 ` Mark Cave-Ayland
2021-07-03 16:29 ` Philippe Mathieu-Daudé
2021-07-04 15:34 ` Mark Cave-Ayland
2021-07-04 2:06 ` Finn Thain
2021-07-03 14:19 ` [RFC PATCH 3/6] dp8393x: Restrict bus access to 16/32-bit operations Philippe Mathieu-Daudé
2021-07-03 14:52 ` Mark Cave-Ayland [this message]
2021-07-04 14:45 ` Mark Cave-Ayland
2021-07-03 14:19 ` [RFC PATCH 4/6] dp8393x: Store CAM registers as 16-bit Philippe Mathieu-Daudé
2021-07-03 14:56 ` Mark Cave-Ayland
2021-07-04 14:48 ` Mark Cave-Ayland
2021-07-06 17:29 ` Philippe Mathieu-Daudé
2021-07-06 19:27 ` Mark Cave-Ayland
2021-07-03 14:19 ` [PATCH 5/6] dp8393x: Replace address_space_rw(is_write=1) by address_space_write() Philippe Mathieu-Daudé
2021-07-03 14:57 ` Mark Cave-Ayland
2021-07-04 14:49 ` Mark Cave-Ayland
2021-07-03 14:19 ` [RFC PATCH 6/6] dp8393x: Rewrite dp8393x_get() / dp8393x_put() Philippe Mathieu-Daudé
2021-07-03 15:00 ` Mark Cave-Ayland
2021-07-03 15:04 ` Philippe Mathieu-Daudé
2021-07-04 1:46 ` Finn Thain
2021-07-04 15:07 ` Mark Cave-Ayland
2021-07-05 1:36 ` Finn Thain
2021-07-05 6:34 ` Mark Cave-Ayland
2021-07-07 1:30 ` Finn Thain
2021-07-07 10:12 ` Mark Cave-Ayland
2021-07-09 9:13 ` Finn Thain
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