From: Sagar Ghuge <sagar.ghuge@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/icl, tgl: whitelist COMMON_SLICE_CHICKEN3 register
Date: Fri, 5 Feb 2021 10:48:54 -0800 [thread overview]
Message-ID: <73c0eb51-a40f-e4c7-d693-175e139c83c0@intel.com> (raw)
In-Reply-To: <161253202745.17965.9984860116785355664@build.alporthouse.com>
On 2/5/21 5:33 AM, Chris Wilson wrote:
> Quoting Sagar Ghuge (2021-02-05 00:33:10)
>> Adding this register to whitelist will allow UMD to toggle State Cache
>> Perf fix disable chicken bit.
>>
>> "If this bit is enabled, RCC uses BTP+BTI as address tag in its state
>> cache instead of BTI only"
>>
>> which will lead to dropping unnecessary render target flushes and stall
>> on scoreboard.
>
> The rest of the register looks safe to expose, and it passes our sanity
> checks that the register is local to the context and should not affect
> others.
>
>> Bspec: 11333
>> Bspec: 45829
>>
>> Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
>
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
>
Thank you!
> The only missing piece of the puzzle that Joonas will require is a
> Link: to a reviewed userspace patch/MR to confirm the uABI.
Link to MR:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8766
> -Chris
>
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prev parent reply other threads:[~2021-02-05 18:49 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-05 0:33 [Intel-gfx] [PATCH] drm/i915/icl, tgl: whitelist COMMON_SLICE_CHICKEN3 register Sagar Ghuge
2021-02-05 3:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-02-05 13:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-02-05 13:33 ` [Intel-gfx] [PATCH] " Chris Wilson
2021-02-05 18:48 ` Sagar Ghuge [this message]
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