Re: [PATCH 7/9] drm/i915: Check infoframe state more diligently.

From: "Konduru, Chandra" <chandra.konduru@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 7/9] drm/i915: Check infoframe state more	diligently.
Date: Mon, 1 Jun 2015 22:57:32 +0000	[thread overview]
Message-ID: <76A9B330A4D78C4D99CB292C4CC06C0E36FEEEF8@fmsmsx101.amr.corp.intel.com> (raw)
In-Reply-To: <1430834787-10255-8-git-send-email-ville.syrjala@linux.intel.com>


> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
> ville.syrjala@linux.intel.com
> Sent: Tuesday, May 05, 2015 7:06 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 7/9] drm/i915: Check infoframe state more
> diligently.
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Check that the DIP is enabled on the right port on IBX and VLV/CHV as
> we're doing on g4x, and also check for all the infoframe enable bits on
> all platforms.
> 
> Eventually we should track each infoframe type independently, and also
> their contents. This is a small step in that direction as .infoframe_enabled()
> return value could be easily turned into a bitmask.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_hdmi.c | 44 ++++++++++++++++++++++++++++------
> -----
>  1 file changed, 32 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index 03b4759..ce595c3 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -174,10 +174,14 @@ static bool g4x_infoframe_enabled(struct
> drm_encoder *encoder)
>  	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
>  	u32 val = I915_READ(VIDEO_DIP_CTL);
> 
> -	if (VIDEO_DIP_PORT(intel_dig_port->port) == (val &
> VIDEO_DIP_PORT_MASK))
> -		return val & VIDEO_DIP_ENABLE;
> +	if ((val & VIDEO_DIP_ENABLE) == 0)
> +		return false;
> 
> -	return false;
> +	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port-
> >port))
> +		return false;
> +
> +	return val & (VIDEO_DIP_ENABLE_AVI |
> +		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
>  }
> 
>  static void ibx_write_infoframe(struct drm_encoder *encoder,
> @@ -227,10 +231,15 @@ static bool ibx_infoframe_enabled(struct
> drm_encoder *encoder)
>  	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
>  	u32 val = I915_READ(reg);
> 
> -	if (VIDEO_DIP_PORT(intel_dig_port->port) == (val &
> VIDEO_DIP_PORT_MASK))
> -		return val & VIDEO_DIP_ENABLE;
> +	if ((val & VIDEO_DIP_ENABLE) == 0)
> +		return false;
> 
> -	return false;
> +	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port-
> >port))
> +		return false;
> +
> +	return val & (VIDEO_DIP_ENABLE_AVI |
> +		      VIDEO_DIP_ENABLE_VENDOR |
> VIDEO_DIP_ENABLE_GAMUT |
> +		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
>  }
> 
>  static void cpt_write_infoframe(struct drm_encoder *encoder,
> @@ -282,7 +291,12 @@ static bool cpt_infoframe_enabled(struct drm_encoder
> *encoder)
>  	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
>  	u32 val = I915_READ(reg);
> 
> -	return val & VIDEO_DIP_ENABLE;
> +	if ((val & VIDEO_DIP_ENABLE) == 0)
> +		return false;
> +
> +	return val & (VIDEO_DIP_ENABLE_AVI |
> +		      VIDEO_DIP_ENABLE_VENDOR |
> VIDEO_DIP_ENABLE_GAMUT |
> +		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
>  }
> 
>  static void vlv_write_infoframe(struct drm_encoder *encoder,
> @@ -332,10 +346,15 @@ static bool vlv_infoframe_enabled(struct
> drm_encoder *encoder)
>  	int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
>  	u32 val = I915_READ(reg);
> 
> -	if (VIDEO_DIP_PORT(intel_dig_port->port) == (val &
> VIDEO_DIP_PORT_MASK))
> -		return val & VIDEO_DIP_ENABLE;
> +	if ((val & VIDEO_DIP_ENABLE) == 0)
> +		return false;
> 
> -	return false;
> +	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port-
> >port))
> +		return false;
> +
> +	return val & (VIDEO_DIP_ENABLE_AVI |
> +		      VIDEO_DIP_ENABLE_VENDOR |
> VIDEO_DIP_ENABLE_GAMUT |
> +		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
>  }
> 
>  static void hsw_write_infoframe(struct drm_encoder *encoder,
> @@ -383,8 +402,9 @@ static bool hsw_infoframe_enabled(struct drm_encoder
> *encoder)
>  	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config-
> >cpu_transcoder);
>  	u32 val = I915_READ(ctl_reg);
> 
> -	return val & (VIDEO_DIP_ENABLE_AVI_HSW |
> VIDEO_DIP_ENABLE_SPD_HSW |
> -		      VIDEO_DIP_ENABLE_VS_HSW);
> +	return val & (VIDEO_DIP_ENABLE_VSC_HSW |
> VIDEO_DIP_ENABLE_AVI_HSW |
> +		      VIDEO_DIP_ENABLE_GCP_HSW |
> VIDEO_DIP_ENABLE_VS_HSW |
> +		      VIDEO_DIP_ENABLE_GMP_HSW |
> VIDEO_DIP_ENABLE_SPD_HSW);
>  }
> 
Reviewed-by: Chandra Konduru <Chandra.konduru@intel.com>

>  /*
> --
> 2.0.5
> 
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