From: Tom Rix <trix@redhat.com>
To: Lizhi Hou <lizhi.hou@xilinx.com>, linux-kernel@vger.kernel.org
Cc: Lizhi Hou <lizhih@xilinx.com>,
linux-fpga@vger.kernel.org, maxz@xilinx.com,
sonal.santan@xilinx.com, michal.simek@xilinx.com,
stefanos@xilinx.com, devicetree@vger.kernel.org, mdf@kernel.org,
robh@kernel.org, Max Zhen <max.zhen@xilinx.com>
Subject: Re: [PATCH V3 XRT Alveo 15/18] fpga: xrt: clock frequence counter platform driver
Date: Sat, 6 Mar 2021 07:25:06 -0800 [thread overview]
Message-ID: <85c34149-ccb4-31c9-4a7d-477b30effad2@redhat.com> (raw)
In-Reply-To: <20210218064019.29189-16-lizhih@xilinx.com>
On 2/17/21 10:40 PM, Lizhi Hou wrote:
> Add clock frequence counter driver. Clock frequence counter is
> a hardware function discovered by walking xclbin metadata. A platform
> device node will be created for it. Other part of driver can read the
> actual clock frequence through clock frequence counter driver.
>
> Signed-off-by: Sonal Santan <sonal.santan@xilinx.com>
> Signed-off-by: Max Zhen <max.zhen@xilinx.com>
> Signed-off-by: Lizhi Hou <lizhih@xilinx.com>
> ---
> drivers/fpga/xrt/include/xleaf/clkfreq.h | 23 +++
> drivers/fpga/xrt/lib/xleaf/clkfreq.c | 221 +++++++++++++++++++++++
> 2 files changed, 244 insertions(+)
> create mode 100644 drivers/fpga/xrt/include/xleaf/clkfreq.h
> create mode 100644 drivers/fpga/xrt/lib/xleaf/clkfreq.c
>
> diff --git a/drivers/fpga/xrt/include/xleaf/clkfreq.h b/drivers/fpga/xrt/include/xleaf/clkfreq.h
> new file mode 100644
> index 000000000000..29fc45e8a31b
> --- /dev/null
> +++ b/drivers/fpga/xrt/include/xleaf/clkfreq.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Header file for XRT Clock Counter Leaf Driver
> + *
> + * Copyright (C) 2020-2021 Xilinx, Inc.
> + *
> + * Authors:
> + * Lizhi Hou <Lizhi.Hou@xilinx.com>
> + */
> +
> +#ifndef _XRT_CLKFREQ_H_
> +#define _XRT_CLKFREQ_H_
> +
> +#include "xleaf.h"
> +
> +/*
> + * CLKFREQ driver IOCTL calls.
> + */
> +enum xrt_clkfreq_ioctl_cmd {
> + XRT_CLKFREQ_READ = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */
> +};
> +
> +#endif /* _XRT_CLKFREQ_H_ */
> diff --git a/drivers/fpga/xrt/lib/xleaf/clkfreq.c b/drivers/fpga/xrt/lib/xleaf/clkfreq.c
> new file mode 100644
> index 000000000000..2482dd2cff47
> --- /dev/null
> +++ b/drivers/fpga/xrt/lib/xleaf/clkfreq.c
> @@ -0,0 +1,221 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Xilinx Alveo FPGA Clock Frequency Counter Driver
> + *
> + * Copyright (C) 2020-2021 Xilinx, Inc.
> + *
> + * Authors:
> + * Lizhi Hou<Lizhi.Hou@xilinx.com>
> + */
> +
> +#include <linux/mod_devicetable.h>
> +#include <linux/platform_device.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include "metadata.h"
> +#include "xleaf.h"
> +#include "xleaf/clkfreq.h"
> +
> +#define CLKFREQ_ERR(clkfreq, fmt, arg...) \
> + xrt_err((clkfreq)->pdev, fmt "\n", ##arg)
> +#define CLKFREQ_WARN(clkfreq, fmt, arg...) \
> + xrt_warn((clkfreq)->pdev, fmt "\n", ##arg)
> +#define CLKFREQ_INFO(clkfreq, fmt, arg...) \
> + xrt_info((clkfreq)->pdev, fmt "\n", ##arg)
> +#define CLKFREQ_DBG(clkfreq, fmt, arg...) \
> + xrt_dbg((clkfreq)->pdev, fmt "\n", ##arg)
> +
> +#define XRT_CLKFREQ "xrt_clkfreq"
> +
> +#define OCL_CLKWIZ_STATUS_MASK 0xffff
> +
> +#define OCL_CLKWIZ_STATUS_MEASURE_START 0x1
> +#define OCL_CLKWIZ_STATUS_MEASURE_DONE 0x2
> +#define OCL_CLK_FREQ_COUNTER_OFFSET 0x8
> +#define OCL_CLK_FREQ_V5_COUNTER_OFFSET 0x10
> +#define OCL_CLK_FREQ_V5_CLK0_ENABLED 0x10000
Similar to earlier, OCL -> XRT_CLKFREQ
Use regmap
> +
> +struct clkfreq {
> + struct platform_device *pdev;
> + void __iomem *clkfreq_base;
> + const char *clkfreq_ep_name;
> + struct mutex clkfreq_lock; /* clock counter dev lock */
> +};
> +
> +static inline u32 reg_rd(struct clkfreq *clkfreq, u32 offset)
> +{
> + return ioread32(clkfreq->clkfreq_base + offset);
> +}
> +
> +static inline void reg_wr(struct clkfreq *clkfreq, u32 val, u32 offset)
> +{
> + iowrite32(val, clkfreq->clkfreq_base + offset);
> +}
> +
> +static u32 clkfreq_read(struct clkfreq *clkfreq)
> +{
failure returns 0, it would be better if -EINVAL or similar was returned.
and u32 *freq added as a function parameter
> + u32 freq = 0, status;
> + int times = 10;
10 is a config parameter, should be a #define
> +
> + mutex_lock(&clkfreq->clkfreq_lock);
> + reg_wr(clkfreq, OCL_CLKWIZ_STATUS_MEASURE_START, 0);
> + while (times != 0) {
> + status = reg_rd(clkfreq, 0);
> + if ((status & OCL_CLKWIZ_STATUS_MASK) ==
> + OCL_CLKWIZ_STATUS_MEASURE_DONE)
> + break;
> + mdelay(1);
> + times--;
> + };
> + if (times > 0) {
I do not like tristate setting, convert to if-else
> + freq = (status & OCL_CLK_FREQ_V5_CLK0_ENABLED) ?
> + reg_rd(clkfreq, OCL_CLK_FREQ_V5_COUNTER_OFFSET) :
> + reg_rd(clkfreq, OCL_CLK_FREQ_COUNTER_OFFSET);
> + }
> + mutex_unlock(&clkfreq->clkfreq_lock);
> +
> + return freq;
> +}
> +
> +static ssize_t freq_show(struct device *dev, struct device_attribute *attr, char *buf)
> +{
> + struct clkfreq *clkfreq = platform_get_drvdata(to_platform_device(dev));
> + u32 freq;
> + ssize_t count;
> +
> + freq = clkfreq_read(clkfreq);
unchecked error
> + count = snprintf(buf, 64, "%d\n", freq);
%u
> +
> + return count;
> +}
> +static DEVICE_ATTR_RO(freq);
> +
> +static struct attribute *clkfreq_attrs[] = {
> + &dev_attr_freq.attr,
> + NULL,
> +};
> +
> +static struct attribute_group clkfreq_attr_group = {
> + .attrs = clkfreq_attrs,
> +};
> +
> +static int
> +xrt_clkfreq_leaf_ioctl(struct platform_device *pdev, u32 cmd, void *arg)
> +{
> + struct clkfreq *clkfreq;
> + int ret = 0;
> +
> + clkfreq = platform_get_drvdata(pdev);
> +
> + switch (cmd) {
> + case XRT_XLEAF_EVENT:
> + /* Does not handle any event. */
> + break;
> + case XRT_CLKFREQ_READ: {
brace not needed
> + *(u32 *)arg = clkfreq_read(clkfreq);
Unchecked error
> + break;
> + }
> + default:
> + xrt_err(pdev, "unsupported cmd %d", cmd);
> + return -EINVAL;
> + }
> +
> + return ret;
> +}
> +
> +static int clkfreq_remove(struct platform_device *pdev)
> +{
> + struct clkfreq *clkfreq;
> +
> + clkfreq = platform_get_drvdata(pdev);
> + if (!clkfreq) {
> + xrt_err(pdev, "driver data is NULL");
> + return -EINVAL;
> + }
> +
> + platform_set_drvdata(pdev, NULL);
> + devm_kfree(&pdev->dev, clkfreq);
> +
> + CLKFREQ_INFO(clkfreq, "successfully removed clkfreq subdev");
> + return 0;
> +}
> +
> +static int clkfreq_probe(struct platform_device *pdev)
> +{
> + struct clkfreq *clkfreq = NULL;
> + struct resource *res;
> + int ret;
> +
> + clkfreq = devm_kzalloc(&pdev->dev, sizeof(*clkfreq), GFP_KERNEL);
> + if (!clkfreq)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, clkfreq);
> + clkfreq->pdev = pdev;
> + mutex_init(&clkfreq->clkfreq_lock);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + clkfreq->clkfreq_base = ioremap(res->start, res->end - res->start + 1);
> + if (!clkfreq->clkfreq_base) {
> + CLKFREQ_ERR(clkfreq, "map base %pR failed", res);
> + ret = -EFAULT;
> + goto failed;
> + }
> + clkfreq->clkfreq_ep_name = res->name;
> +
> + ret = sysfs_create_group(&pdev->dev.kobj, &clkfreq_attr_group);
> + if (ret) {
> + CLKFREQ_ERR(clkfreq, "create clkfreq attrs failed: %d", ret);
> + goto failed;
> + }
> +
> + CLKFREQ_INFO(clkfreq, "successfully initialized clkfreq subdev");
> +
> + return 0;
> +
> +failed:
> + clkfreq_remove(pdev);
> + return ret;
> +}
> +
> +static struct xrt_subdev_endpoints xrt_clkfreq_endpoints[] = {
> + {
> + .xse_names = (struct xrt_subdev_ep_names[]) {
> + { .regmap_name = "freq_cnt" },
name should be closer to filename, maybe 'clock_frequency' or 'clkfreq'
Tom
> + { NULL },
> + },
> + .xse_min_ep = 1,
> + },
> + { 0 },
> +};
> +
> +static struct xrt_subdev_drvdata xrt_clkfreq_data = {
> + .xsd_dev_ops = {
> + .xsd_ioctl = xrt_clkfreq_leaf_ioctl,
> + },
> +};
> +
> +static const struct platform_device_id xrt_clkfreq_table[] = {
> + { XRT_CLKFREQ, (kernel_ulong_t)&xrt_clkfreq_data },
> + { },
> +};
> +
> +static struct platform_driver xrt_clkfreq_driver = {
> + .driver = {
> + .name = XRT_CLKFREQ,
> + },
> + .probe = clkfreq_probe,
> + .remove = clkfreq_remove,
> + .id_table = xrt_clkfreq_table,
> +};
> +
> +void clkfreq_leaf_init_fini(bool init)
> +{
> + if (init) {
> + xleaf_register_driver(XRT_SUBDEV_CLKFREQ,
> + &xrt_clkfreq_driver, xrt_clkfreq_endpoints);
> + } else {
> + xleaf_unregister_driver(XRT_SUBDEV_CLKFREQ);
> + }
> +}
next prev parent reply other threads:[~2021-03-06 15:26 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-18 6:40 [PATCH V3 XRT Alveo 00/18] XRT Alveo driver overview Lizhi Hou
2021-02-18 6:40 ` [PATCH V3 XRT Alveo 01/18] Documentation: fpga: Add a document describing XRT Alveo drivers Lizhi Hou
2021-02-19 22:26 ` Tom Rix
2021-03-01 6:48 ` Sonal Santan
2021-03-06 17:19 ` Moritz Fischer
2021-03-08 20:12 ` Sonal Santan
2021-02-18 6:40 ` [PATCH V3 XRT Alveo 02/18] fpga: xrt: driver metadata helper functions Lizhi Hou
2021-02-20 17:07 ` Tom Rix
2021-02-23 6:05 ` Lizhi Hou
2021-02-23 1:23 ` Fernando Pacheco
2021-02-25 20:27 ` Lizhi Hou
2021-02-18 6:40 ` [PATCH V3 XRT Alveo 03/18] fpga: xrt: xclbin file " Lizhi Hou
2021-02-21 17:12 ` Tom Rix
2021-02-21 18:33 ` Moritz Fischer
2021-03-06 1:13 ` Lizhi Hou
2021-02-26 21:23 ` Lizhi Hou
2021-02-28 16:54 ` Tom Rix
2021-03-02 0:25 ` Lizhi Hou
2021-03-02 15:14 ` Moritz Fischer
2021-03-04 18:53 ` Lizhi Hou
2021-02-18 6:40 ` [PATCH V3 XRT Alveo 04/18] fpga: xrt: xrt-lib platform driver manager Lizhi Hou
2021-02-21 20:39 ` Moritz Fischer
2021-03-01 20:34 ` Max Zhen
2021-02-22 15:05 ` Tom Rix
2021-02-23 3:35 ` Moritz Fischer
2021-03-03 17:20 ` Max Zhen
2021-02-18 6:40 ` [PATCH V3 XRT Alveo 05/18] fpga: xrt: group platform driver Lizhi Hou
2021-02-22 18:50 ` Tom Rix
2021-02-26 21:57 ` Max Zhen
2021-02-18 6:40 ` [PATCH V3 XRT Alveo 06/18] fpga: xrt: platform driver infrastructure Lizhi Hou
2021-02-25 21:59 ` Tom Rix
[not found] ` <13e9a311-2d04-ba65-3ed2-f9f1834c37de@xilinx.com>
2021-03-08 20:36 ` Max Zhen
2021-02-18 6:40 ` [PATCH V3 XRT Alveo 07/18] fpga: xrt: management physical function driver (root) Lizhi Hou
2021-02-26 15:01 ` Tom Rix
2021-02-26 17:56 ` Moritz Fischer
2021-03-16 20:29 ` Max Zhen
2021-03-17 21:08 ` Tom Rix
2021-03-18 0:44 ` Max Zhen
2021-02-18 6:40 ` [PATCH V3 XRT Alveo 08/18] fpga: xrt: main platform driver for management function device Lizhi Hou
2021-02-26 17:22 ` Tom Rix
2021-03-16 21:23 ` Lizhi Hou
2021-03-17 21:12 ` Tom Rix
2021-02-18 6:40 ` [PATCH V3 XRT Alveo 09/18] fpga: xrt: fpga-mgr and region implementation for xclbin download Lizhi Hou
2021-02-28 16:36 ` Tom Rix
2021-03-04 17:50 ` Lizhi Hou
2021-02-18 6:40 ` [PATCH V3 XRT Alveo 10/18] fpga: xrt: VSEC platform driver Lizhi Hou
2021-03-01 19:01 ` Tom Rix
2021-03-05 19:58 ` Lizhi Hou
2021-02-18 6:40 ` [PATCH V3 XRT Alveo 11/18] fpga: xrt: UCS " Lizhi Hou
2021-03-02 16:09 ` Tom Rix
2021-03-10 20:24 ` Lizhi Hou
2021-02-18 6:40 ` [PATCH V3 XRT Alveo 12/18] fpga: xrt: ICAP " Lizhi Hou
2021-02-21 20:24 ` Moritz Fischer
2021-03-02 18:26 ` Lizhi Hou
2021-03-03 15:12 ` Tom Rix
2021-03-17 20:56 ` Lizhi Hou
2021-02-18 6:40 ` [PATCH V3 XRT Alveo 13/18] fpga: xrt: devctl " Lizhi Hou
2021-03-04 13:39 ` Tom Rix
2021-03-16 23:54 ` Lizhi Hou
2021-03-17 21:16 ` Tom Rix
2021-02-18 6:40 ` [PATCH V3 XRT Alveo 14/18] fpga: xrt: clock " Lizhi Hou
2021-03-05 15:23 ` Tom Rix
2021-03-11 0:12 ` Lizhi Hou
2021-02-18 6:40 ` [PATCH V3 XRT Alveo 15/18] fpga: xrt: clock frequence counter " Lizhi Hou
2021-03-06 15:25 ` Tom Rix [this message]
2021-03-12 23:43 ` Lizhi Hou
2021-02-18 6:40 ` [PATCH V3 XRT Alveo 16/18] fpga: xrt: DDR calibration " Lizhi Hou
2021-02-21 20:21 ` Moritz Fischer
2021-03-06 15:34 ` Tom Rix
2021-03-13 0:45 ` Lizhi Hou
2021-02-18 6:40 ` [PATCH V3 XRT Alveo 17/18] fpga: xrt: partition isolation " Lizhi Hou
2021-02-21 20:36 ` Moritz Fischer
2021-03-16 20:38 ` Lizhi Hou
2021-03-06 15:54 ` Tom Rix
2021-03-13 6:53 ` Lizhi Hou
2021-02-18 6:40 ` [PATCH V3 XRT Alveo 18/18] fpga: xrt: Kconfig and Makefile updates for XRT drivers Lizhi Hou
2021-02-18 9:02 ` kernel test robot
2021-02-18 9:02 ` kernel test robot
2021-02-18 19:50 ` kernel test robot
2021-02-18 19:50 ` kernel test robot
2021-02-21 14:57 ` Tom Rix
2021-02-21 18:39 ` Moritz Fischer
2021-02-28 20:52 ` Sonal Santan
2021-02-18 13:52 ` [PATCH V3 XRT Alveo 00/18] XRT Alveo driver overview Tom Rix
2021-02-19 5:15 ` Lizhi Hou
2021-02-21 20:43 ` Moritz Fischer
2021-03-01 18:29 ` Lizhi Hou
2021-03-03 6:49 ` Joe Perches
2021-03-03 23:15 ` Moritz Fischer
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