From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/5] drm/i915: Use simplest form for flushing the single cacheline in the HWS
Date: Tue, 16 Feb 2016 14:58:56 +0200 [thread overview]
Message-ID: <874md8reun.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <1455623268-10023-5-git-send-email-chris@chris-wilson.co.uk>
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Rather than call a function to compute the matching cachelines and
> clflush them, just call the clflush *instruction* directly. We also know
> that we can use the unpatched plain clflush rather than the clflushopt
> alternative.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index dfb14bfe5bc8..e2b2dc2c2f49 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -393,8 +393,9 @@ intel_ring_sync_index(struct intel_engine_cs *ring,
> static inline void
> intel_flush_status_page(struct intel_engine_cs *ring, int reg)
> {
> - drm_clflush_virt_range(&ring->status_page.page_addr[reg],
> - sizeof(uint32_t));
> + mb();
Checkpatch complains about memory barrier without comments.
Don't we need to check cpu_has_clflush?
-Mika
> + clflush(&ring->status_page.page_addr[reg]);
> + mb();
> }
>
> static inline u32
> --
> 2.7.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2016-02-16 13:00 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-16 11:47 Missed interrupt false positives mitigation Chris Wilson
2016-02-16 11:47 ` [PATCH 1/5] drm/i915: Remove forcewake dance from seqno/irq barrier on legacy gen6+ Chris Wilson
2016-02-16 11:47 ` [PATCH 2/5] drm/i915: Separate out the seqno-barrier from engine->get_seqno Chris Wilson
2016-02-16 12:51 ` Mika Kuoppala
2016-02-16 11:47 ` [PATCH 3/5] drm/i915: Harden detection of missed interrupts Chris Wilson
2016-02-16 12:51 ` Mika Kuoppala
2016-02-16 11:47 ` [PATCH 4/5] drm/i915: Use simplest form for flushing the single cacheline in the HWS Chris Wilson
2016-02-16 12:58 ` Mika Kuoppala [this message]
2016-02-19 11:49 ` Chris Wilson
2016-02-19 13:42 ` Mika Kuoppala
2016-02-16 11:47 ` [PATCH 5/5] drm/i915: Replace manual barrier() with READ_ONCE() in HWS accessor Chris Wilson
2016-02-16 12:14 ` ✗ Fi.CI.BAT: warning for series starting with [1/5] drm/i915: Remove forcewake dance from seqno/irq barrier on legacy gen6+ Patchwork
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