Re: [PATCH v1 0/1] Improved Memory Tier Creation for CPUless NUMA Nodes

From: "Huang, Ying" <ying.huang@intel.com>
To: "Ho-Ren (Jack) Chuang" <horenchuang@bytedance.com>
Cc: "Hao Xiang" <hao.xiang@bytedance.com>,
	 "Gregory Price" <gourry.memverge@gmail.com>,
	 aneesh.kumar@linux.ibm.com, mhocko@suse.com,  tj@kernel.org,
	 john@jagalactic.com,  "Eishan Mirakhur" <emirakhur@micron.com>,
	 "Vinicius Tavares Petrucci" <vtavarespetr@micron.com>,
	 "Ravis OpenSrc" <Ravis.OpenSrc@micron.com>,
	"Alistair Popple" <apopple@nvidia.com>,
	 "Rafael J. Wysocki" <rafael@kernel.org>,
	 Len Brown <lenb@kernel.org>,
	 Andrew Morton <akpm@linux-foundation.org>,
	 Dave Jiang <dave.jiang@intel.com>,
	 Dan Williams <dan.j.williams@intel.com>,
	 Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	 linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org,
	 linux-mm@kvack.org,  "Ho-Ren (Jack) Chuang" <horenc@vt.edu>,
	 "Ho-Ren (Jack) Chuang" <horenchuang@gmail.com>,
	linux-cxl@vger.kernel.org,  qemu-devel@nongnu.org
Subject: Re: [PATCH v1 0/1] Improved Memory Tier Creation for CPUless NUMA Nodes
Date: Mon, 04 Mar 2024 10:45:02 +0800	[thread overview]
Message-ID: <87frx6btqp.fsf@yhuang6-desk2.ccr.corp.intel.com> (raw)
In-Reply-To: <20240301082248.3456086-1-horenchuang@bytedance.com> (Ho-Ren Chuang's message of "Fri, 1 Mar 2024 08:22:44 +0000")

"Ho-Ren (Jack) Chuang" <horenchuang@bytedance.com> writes:

> The memory tiering component in the kernel is functionally useless for
> CPUless memory/non-DRAM devices like CXL1.1 type3 memory because the nodes
> are lumped together in the DRAM tier.
> https://lore.kernel.org/linux-mm/PH0PR08MB7955E9F08CCB64F23963B5C3A860A@PH0PR08MB7955.namprd08.prod.outlook.com/T/

I think that it's unfair to call it "useless".  Yes, it doesn't work if
the CXL memory device are not enumerate via drivers/dax/kmem.c.  So,
please be specific about in which cases it doesn't work instead of too
general "useless".

> This patchset automatically resolves the issues. It delays the initialization
> of memory tiers for CPUless NUMA nodes until they obtain HMAT information
> at boot time, eliminating the need for user intervention.
> If no HMAT specified, it falls back to using `default_dram_type`.
>
> Example usecase:
> We have CXL memory on the host, and we create VMs with a new system memory
> device backed by host CXL memory. We inject CXL memory performance attributes
> through QEMU, and the guest now sees memory nodes with performance attributes
> in HMAT. With this change, we enable the guest kernel to construct
> the correct memory tiering for the memory nodes.
>
> Ho-Ren (Jack) Chuang (1):
>   memory tier: acpi/hmat: create CPUless memory tiers after obtaining
>     HMAT info
>
>  drivers/acpi/numa/hmat.c     |  3 ++
>  include/linux/memory-tiers.h |  6 +++
>  mm/memory-tiers.c            | 76 ++++++++++++++++++++++++++++++++----
>  3 files changed, 77 insertions(+), 8 deletions(-)

--
Best Regards,
Huang, Ying