All of lore.kernel.org
 help / color / mirror / Atom feed
From: Jani Nikula <jani.nikula@intel.com>
To: Ramalingam C <ramalingam.c@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3] drm/i915/hdcp: Update CP as per the kernel internal state
Date: Mon, 20 Jan 2020 15:02:46 +0200	[thread overview]
Message-ID: <87pnfeffgp.fsf@intel.com> (raw)
In-Reply-To: <20200120115134.GB15991@intel.com>

On Mon, 20 Jan 2020, Ramalingam C <ramalingam.c@intel.com> wrote:
> hdcp->value is used to track the internal transistions during the link
> failure and re-establishing it. When ever kernel want to update the
> "content protection" we take the required locks and update the property
> state along with uevent.

My point is this: How many states does your state machine need?

Considering the tri-state content_protection and tri-state hdcp->value,
you have 9 possible states and 362880 transitions. Add the new flag from
this patch, and you have 18 possible states and 6e15 transitions.

Obviously you don't need or use that many states or transitions, but you
need the code to limit the states and the transitions. You need the
review to ensure any changes take into account all the possible states
and transitions.

I've already noted one possible scenario in the proposed patch where
stuff goes out of sync, and I don't know what's really going to happen.

---

So maybe I don't understand what the hdcp code does, but then maybe you
shouldn't ask me to have a look at it... ;) I'm trying to point out why
I think it's maybe difficult to understand, and why I think adding
another flag might make it more difficult to maintain.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-01-20 13:02 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-20  5:49 [Intel-gfx] [PATCH v3] drm/i915/hdcp: Update CP as per the kernel internal state Anshuman Gupta
2020-01-20  6:54 ` Ramalingam C
2020-01-20 10:29   ` Jani Nikula
2020-01-20 11:00     ` Ramalingam C
2020-01-20 11:24       ` Jani Nikula
2020-01-20 11:51         ` Ramalingam C
2020-01-20 13:02           ` Jani Nikula [this message]
2020-01-21  0:49             ` Ramalingam C
2020-01-20  6:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2020-01-20 10:20 ` [Intel-gfx] [PATCH v3] " Jani Nikula
2020-01-21  0:39 ` Ramalingam C
2020-01-21 12:15   ` Jani Nikula
2020-01-22 14:11     ` Ramalingam C
2020-01-22 14:56       ` Jani Nikula
2020-01-24  4:20         ` Anshuman Gupta
2020-01-21  2:55 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
2020-06-30  8:20 [Intel-gfx] [PATCH v3] " Anshuman Gupta
2020-06-30 10:00 ` Jani Nikula
2020-07-01  7:59   ` Shankar, Uma
2020-07-01  8:01     ` Shankar, Uma
2020-07-08  8:25       ` Anshuman Gupta
2020-07-08  9:58         ` Ramalingam C
2020-06-30 10:01 ` Jani Nikula
2020-06-30 13:30 ` Ramalingam C

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=87pnfeffgp.fsf@intel.com \
    --to=jani.nikula@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=ramalingam.c@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.