From: Thomas Gleixner <tglx@linutronix.de>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: LKML <linux-kernel@vger.kernel.org>,
Alex Williamson <alex.williamson@redhat.com>, "Raj\,
Ashok" <ashok.raj@intel.com>,
"David S. Miller" <davem@davemloft.net>,
Bjorn Helgaas <bhelgaas@google.com>,
linux-pci@vger.kernel.org, Kevin Tian <kevin.tian@intel.com>,
Marc Zyngier <maz@kernel.org>, Ingo Molnar <mingo@kernel.org>,
x86@kernel.org
Subject: Re: [patch 1/8] PCI/MSI: Enable and mask MSIX early
Date: Tue, 27 Jul 2021 22:33:35 +0200 [thread overview]
Message-ID: <87r1fjpkdc.ffs@nanos.tec.linutronix.de> (raw)
In-Reply-To: <20210722214329.GA349464@bjorn-Precision-5520>
On Thu, Jul 22 2021 at 16:43, Bjorn Helgaas wrote:
> s/MSIX/MSI-X/ in subject
Sure.
> On Wed, Jul 21, 2021 at 09:11:27PM +0200, Thomas Gleixner wrote:
>> The ordering of MSI-X enable in hardware is disfunctional:
>
> s/disfunctional/dysfunctional/, isn't English wonderful ;)
Yes and I'm never going to master it.
>> 1) MSI-X is disabled in the control register
>> 2) Various setup functions
>> 3) pci_msi_setup_msi_irqs() is invoked which ends up accessing
>> the MSI-X table entries
>> 4) MSI-X is enabled and masked in the control register with the
>> comment that enabling is required for some hardware to access
>> the MSI-X table
>>
>> #4 obviously contradicts #3. The history of this is an issue with the NIU
>
> Annoyingly, if you "git rebase" and reword this commit log, it drops
> this line and the one a few lines below because they start with "#".
> Should be obvious, but took me a few iterations to see what was
> happening.
Cute.
Thanks,
tglx
next prev parent reply other threads:[~2021-07-27 20:33 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-21 19:11 [patch 0/8] PCI/MSI, x86: Cure a couple of inconsistencies Thomas Gleixner
2021-07-21 19:11 ` [patch 1/8] PCI/MSI: Enable and mask MSIX early Thomas Gleixner
2021-07-21 21:38 ` Raj, Ashok
2021-07-21 22:51 ` Thomas Gleixner
2021-07-22 21:43 ` Bjorn Helgaas
2021-07-27 20:33 ` Thomas Gleixner [this message]
2021-07-21 19:11 ` [patch 2/8] PCI/MSI: Mask all unused MSI-X entries Thomas Gleixner
2021-07-21 22:23 ` Raj, Ashok
2021-07-21 22:57 ` Thomas Gleixner
2021-07-22 13:46 ` Marc Zyngier
2021-07-28 10:04 ` Thomas Gleixner
2021-07-22 21:45 ` Bjorn Helgaas
2021-07-21 19:11 ` [patch 3/8] PCI/MSI: Enforce that MSI-X table entry is masked for update Thomas Gleixner
2021-07-21 22:32 ` Raj, Ashok
2021-07-21 22:59 ` Thomas Gleixner
2021-07-22 21:46 ` Bjorn Helgaas
2021-07-21 19:11 ` [patch 4/8] PCI/MSI: Enforce MSI[X] entry updates to be visible Thomas Gleixner
2021-07-22 21:48 ` Bjorn Helgaas
[not found] ` <CAHp75VdNi4rMuRz8UrW9Haf_Ge8KmNJ0w9ykheqkVhmpXHTUyg@mail.gmail.com>
2021-07-23 8:14 ` Marc Zyngier
2021-07-21 19:11 ` [patch 5/8] PCI/MSI: Simplify msi_verify_entries() Thomas Gleixner
2021-07-21 19:11 ` [patch 6/8] genirq: Provide IRQCHIP_AFFINITY_PRE_STARTUP Thomas Gleixner
2021-07-22 15:12 ` Marc Zyngier
2021-07-28 10:40 ` Thomas Gleixner
2021-07-21 19:11 ` [patch 7/8] x86/ioapic: Force affinity setup before startup Thomas Gleixner
2021-07-21 19:11 ` [patch 8/8] x86/msi: " Thomas Gleixner
2021-07-21 21:10 ` [patch 0/8] PCI/MSI, x86: Cure a couple of inconsistencies Raj, Ashok
2021-07-21 22:39 ` Thomas Gleixner
2021-07-22 15:17 ` Marc Zyngier
2021-07-22 21:43 ` Bjorn Helgaas
2021-07-27 20:38 ` Thomas Gleixner
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