Re: [PATCH v3 12/20] target/arm: generate xml description of our SVE registers

From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: damien.hedde@greensocs.com,
	Peter Maydell <peter.maydell@linaro.org>,
	luis.machado@linaro.org, qemu-devel@nongnu.org,
	"open list:ARM TCG CPUs" <qemu-arm@nongnu.org>,
	alan.hayward@arm.com
Subject: Re: [PATCH v3 12/20] target/arm: generate xml description of our SVE registers
Date: Thu, 12 Dec 2019 08:24:11 +0000	[thread overview]
Message-ID: <87y2vi0x5g.fsf@linaro.org> (raw)
In-Reply-To: <69e10c48-8bdf-cbe0-3372-815b647f8312@linaro.org>

Richard Henderson <richard.henderson@linaro.org> writes:

> On 12/11/19 9:05 AM, Alex Bennée wrote:
>> +static struct TypeSize vec_lanes[] = {
>
> const.
>
>> +    case 51:
>> +        return gdb_get_reg64(buf, (cpu->env.vfp.zcr_el[1] & 0xf) + 1);
>
> You need to use sve_zcr_len_for_el to get the effective vq.
> Also, I thought vg == 2 * vq.
>  > +    case 51:
>> +    {
>> +        uint64_t val = *(uint64_t *) buf;
>> +        cpu->env.vfp.zcr_el[1] = (val - 1) & 0xf;
>
> You cannot hard-code EL1 without ifdef CONFIG_USER_ONLY.  If the effective vq
> decreases, you must call aarch64_sve_narrow_vq.  You must call
> arm_rebuild_hflags.

Hmm thinking about it this is overriding the kernels competencies - it
should be read only as it is a "virtual" register. Given gdbserver
doesn't use the value and will most likely use dynamic XML we could just
drop it altogether. 

>
>
> r~

-- 
Alex Bennée