From: "Alex Bennée" <alex.bennee@linaro.org>
To: Luis Machado <luis.machado@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>,
"open list:ARM TCG CPUs" <qemu-arm@nongnu.org>,
qemu-devel@nongnu.org
Subject: Re: [PATCH v1 10/20] target/arm: use official org.gnu.gdb.aarch64.sve layout for registers
Date: Mon, 11 Jan 2021 14:36:36 +0000 [thread overview]
Message-ID: <87zh1fo7yd.fsf@linaro.org> (raw)
In-Reply-To: <9ee1443e-821d-9cec-c29a-6111385937ad@linaro.org>
Luis Machado <luis.machado@linaro.org> writes:
> For the record, the layout looks OK to me.
So a Reviewed-by?
> Just a reminder that GDB will soon support bfloat16 types. A patch may
> be pushed this month.
Will we be able to probe for the support - or will an older GDB silently
accept and drop any bfloat16 fields?
>
> On 1/8/21 7:42 PM, Alex Bennée wrote:
>> While GDB can work with any XML description given to it there is
>> special handling for SVE registers on the GDB side which makes the
>> users life a little better. The changes aren't that major and all the
>> registers save the $vg reported the same. All that changes is:
>>
>> - report org.gnu.gdb.aarch64.sve
>> - use gdb nomenclature for names and types
>> - minor re-ordering of the types to match reference
>> - re-enable ieee_half (as we know gdb supports it now)
>> - $vg is now a 64 bit int
>> - check $vN and $zN aliasing in test
>>
>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>> Cc: Luis Machado <luis.machado@linaro.org>
>> Message-Id: <20201218112707.28348-10-alex.bennee@linaro.org>
>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>> ---
>> target/arm/gdbstub.c | 75 ++++++++-------------
>> target/arm/helper.c | 2 +-
>> tests/tcg/aarch64/gdbstub/test-sve-ioctl.py | 11 +++
>> 3 files changed, 41 insertions(+), 47 deletions(-)
>>
>> diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
>> index 866595b4f1..a8fff2a3d0 100644
>> --- a/target/arm/gdbstub.c
>> +++ b/target/arm/gdbstub.c
>> @@ -195,22 +195,17 @@ static const struct TypeSize vec_lanes[] = {
>> { "uint128", 128, 'q', 'u' },
>> { "int128", 128, 'q', 's' },
>> /* 64 bit */
>> + { "ieee_double", 64, 'd', 'f' },
>> { "uint64", 64, 'd', 'u' },
>> { "int64", 64, 'd', 's' },
>> - { "ieee_double", 64, 'd', 'f' },
>> /* 32 bit */
>> + { "ieee_single", 32, 's', 'f' },
>> { "uint32", 32, 's', 'u' },
>> { "int32", 32, 's', 's' },
>> - { "ieee_single", 32, 's', 'f' },
>> /* 16 bit */
>> + { "ieee_half", 16, 'h', 'f' },
>> { "uint16", 16, 'h', 'u' },
>> { "int16", 16, 'h', 's' },
>> - /*
>> - * TODO: currently there is no reliable way of telling
>> - * if the remote gdb actually understands ieee_half so
>> - * we don't expose it in the target description for now.
>> - * { "ieee_half", 16, 'h', 'f' },
>> - */
>> /* bytes */
>> { "uint8", 8, 'b', 'u' },
>> { "int8", 8, 'b', 's' },
>> @@ -223,17 +218,16 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
>> GString *s = g_string_new(NULL);
>> DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
>> g_autoptr(GString) ts = g_string_new("");
>> - int i, bits, reg_width = (cpu->sve_max_vq * 128);
>> + int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
>> info->num = 0;
>> g_string_printf(s, "<?xml version=\"1.0\"?>");
>> g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
>> - g_string_append_printf(s, "<feature name=\"org.qemu.gdb.aarch64.sve\">");
>> + g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
>>
>> /* First define types and totals in a whole VL */
>> for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
>> int count = reg_width / vec_lanes[i].size;
>> - g_string_printf(ts, "vq%d%c%c", count,
>> - vec_lanes[i].sz, vec_lanes[i].suffix);
>> + g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
>> g_string_append_printf(s,
>> "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
>> ts->str, vec_lanes[i].gdb_type, count);
>> @@ -243,39 +237,37 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
>> * signed and potentially float versions of each size from 128 to
>> * 8 bits.
>> */
>> - for (bits = 128; bits >= 8; bits /= 2) {
>> - int count = reg_width / bits;
>> - g_string_append_printf(s, "<union id=\"vq%dn\">", count);
>> - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
>> - if (vec_lanes[i].size == bits) {
>> - g_string_append_printf(s, "<field name=\"%c\" type=\"vq%d%c%c\"/>",
>> - vec_lanes[i].suffix,
>> - count,
>> - vec_lanes[i].sz, vec_lanes[i].suffix);
>> + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
>> + const char suf[] = { 'q', 'd', 's', 'h', 'b' };
>> + g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
>> + for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
>> + if (vec_lanes[j].size == bits) {
>> + g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
>> + vec_lanes[j].suffix,
>> + vec_lanes[j].sz, vec_lanes[j].suffix);
>> }
>> }
>> g_string_append(s, "</union>");
>> }
>> /* And now the final union of unions */
>> - g_string_append(s, "<union id=\"vq\">");
>> - for (bits = 128; bits >= 8; bits /= 2) {
>> - int count = reg_width / bits;
>> - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
>> - if (vec_lanes[i].size == bits) {
>> - g_string_append_printf(s, "<field name=\"%c\" type=\"vq%dn\"/>",
>> - vec_lanes[i].sz, count);
>> - break;
>> - }
>> - }
>> + g_string_append(s, "<union id=\"svev\">");
>> + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
>> + const char suf[] = { 'q', 'd', 's', 'h', 'b' };
>> + g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
>> + suf[i], suf[i]);
>> }
>> g_string_append(s, "</union>");
>>
>> + /* Finally the sve prefix type */
>> + g_string_append_printf(s,
>> + "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
>> + reg_width / 8);
>> +
>> /* Then define each register in parts for each vq */
>> for (i = 0; i < 32; i++) {
>> g_string_append_printf(s,
>> "<reg name=\"z%d\" bitsize=\"%d\""
>> - " regnum=\"%d\" group=\"vector\""
>> - " type=\"vq\"/>",
>> + " regnum=\"%d\" type=\"svev\"/>",
>> i, reg_width, base_reg++);
>> info->num++;
>> }
>> @@ -287,31 +279,22 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
>> " regnum=\"%d\" group=\"float\""
>> " type=\"int\"/>", base_reg++);
>> info->num += 2;
>> - /*
>> - * Predicate registers aren't so big they are worth splitting up
>> - * but we do need to define a type to hold the array of quad
>> - * references.
>> - */
>> - g_string_append_printf(s,
>> - "<vector id=\"vqp\" type=\"uint16\" count=\"%d\"/>",
>> - cpu->sve_max_vq);
>> +
>> for (i = 0; i < 16; i++) {
>> g_string_append_printf(s,
>> "<reg name=\"p%d\" bitsize=\"%d\""
>> - " regnum=\"%d\" group=\"vector\""
>> - " type=\"vqp\"/>",
>> + " regnum=\"%d\" type=\"svep\"/>",
>> i, cpu->sve_max_vq * 16, base_reg++);
>> info->num++;
>> }
>> g_string_append_printf(s,
>> "<reg name=\"ffr\" bitsize=\"%d\""
>> " regnum=\"%d\" group=\"vector\""
>> - " type=\"vqp\"/>",
>> + " type=\"svep\"/>",
>> cpu->sve_max_vq * 16, base_reg++);
>> g_string_append_printf(s,
>> "<reg name=\"vg\" bitsize=\"64\""
>> - " regnum=\"%d\" group=\"vector\""
>> - " type=\"uint32\"/>",
>> + " regnum=\"%d\" type=\"int\"/>",
>> base_reg++);
>> info->num += 2;
>> g_string_append_printf(s, "</feature>");
>> diff --git a/target/arm/helper.c b/target/arm/helper.c
>> index d077dd9ef5..d434044f07 100644
>> --- a/target/arm/helper.c
>> +++ b/target/arm/helper.c
>> @@ -276,7 +276,7 @@ static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
>> * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
>> */
>> int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1;
>> - return gdb_get_reg32(buf, vq * 2);
>> + return gdb_get_reg64(buf, vq * 2);
>> }
>> default:
>> /* gdbstub asked for something out our range */
>> diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py
>> index 972cf73c31..b9ef169c1a 100644
>> --- a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py
>> +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py
>> @@ -40,6 +40,17 @@ class TestBreakpoint(gdb.Breakpoint):
>> except gdb.error:
>> report(False, "checking zregs (out of range)")
>>
>> + # Check the aliased V registers are set and GDB has correctly
>> + # created them for us having recognised and handled SVE.
>> + try:
>> + for i in range(0, 16):
>> + val_z = gdb.parse_and_eval("$z0.b.u[%d]" % i)
>> + val_v = gdb.parse_and_eval("$v0.b.u[%d]" % i)
>> + report(int(val_z) == int(val_v),
>> + "v0.b.u[%d] == z0.b.u[%d]" % (i, i))
>> + except gdb.error:
>> + report(False, "checking vregs (out of range)")
>> +
>>
>> def run_test():
>> "Run through the tests one by one"
>>
--
Alex Bennée
next prev parent reply other threads:[~2021-01-11 14:38 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-08 22:42 [PATCH v1 00/20] gdbstub, semihosting and test/tool updates (pre PR) Alex Bennée
2021-01-08 22:42 ` [PATCH v1 01/20] tests/docker: Remove Debian 9 remnant lines Alex Bennée
2021-01-08 22:42 ` [PATCH v1 02/20] test/guest-debug: echo QEMU command as well Alex Bennée
2021-01-11 15:27 ` Philippe Mathieu-Daudé
2021-01-08 22:42 ` [PATCH v1 03/20] configure: gate our use of GDB to 8.3.1 or above Alex Bennée
2021-01-08 22:42 ` [PATCH v1 04/20] Revert "tests/tcg/multiarch/Makefile.target: Disable run-gdbstub-sha1 test" Alex Bennée
2021-01-08 22:42 ` [PATCH v1 05/20] gdbstub: implement a softmmu based test Alex Bennée
2021-01-08 22:42 ` [PATCH v1 06/20] gdbstub: add support to Xfer:auxv:read: packet Alex Bennée
2021-01-08 22:42 ` [PATCH v1 07/20] gdbstub: drop CPUEnv from gdb_exit() Alex Bennée
2021-01-08 22:42 ` [PATCH v1 08/20] gdbstub: drop gdbserver_cleanup in favour of gdb_exit Alex Bennée
2021-01-08 22:42 ` [PATCH v1 09/20] gdbstub: ensure we clean-up when terminated Alex Bennée
2021-01-08 22:42 ` [PATCH v1 10/20] target/arm: use official org.gnu.gdb.aarch64.sve layout for registers Alex Bennée
2021-01-11 13:20 ` Luis Machado
2021-01-11 14:36 ` Alex Bennée [this message]
2021-01-11 14:50 ` Luis Machado
2021-01-08 22:42 ` [PATCH v1 11/20] Makefile: add GNU global tags support Alex Bennée
2021-01-08 22:42 ` [PATCH v1 12/20] semihosting: Move ARM semihosting code to shared directories Alex Bennée
2021-01-11 15:30 ` Philippe Mathieu-Daudé
2021-01-11 15:32 ` Philippe Mathieu-Daudé
2021-01-11 15:46 ` Philippe Mathieu-Daudé
2021-01-08 22:42 ` [PATCH v1 13/20] semihosting: Change common-semi API to be architecture-independent Alex Bennée
2021-01-11 15:34 ` Philippe Mathieu-Daudé
2021-01-08 22:42 ` [PATCH v1 14/20] semihosting: Change internal common-semi interfaces to use CPUState * Alex Bennée
2021-01-08 22:42 ` [PATCH v1 15/20] semihosting: Support SYS_HEAPINFO when env->boot_info is not set Alex Bennée
2021-01-08 22:42 ` [PATCH v1 16/20] riscv: Add semihosting support Alex Bennée
2021-01-08 22:42 ` Alex Bennée
2021-01-08 23:30 ` Alistair Francis
2021-01-08 23:30 ` Alistair Francis
2021-01-09 0:44 ` Keith Packard via
2021-01-09 0:44 ` Keith Packard
2021-01-08 22:42 ` [PATCH v1 17/20] riscv: Add semihosting support for user mode Alex Bennée
2021-01-08 23:32 ` Alistair Francis
2021-01-11 15:48 ` Philippe Mathieu-Daudé
2021-01-08 22:42 ` [PATCH v1 18/20] semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ Alex Bennée
2021-01-08 22:42 ` [PATCH v1 19/20] semihosting: Implement SYS_TMPNAM Alex Bennée
2021-01-08 22:42 ` [PATCH v1 20/20] semihosting: Implement SYS_ISERROR Alex Bennée
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87zh1fo7yd.fsf@linaro.org \
--to=alex.bennee@linaro.org \
--cc=luis.machado@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.