From: Fredrik Noring <noring@nocrew.org>
To: linux-mips@vger.kernel.org
Subject: [PATCH 027/120] MIPS: PS2: DMAC: Define DMA controller registers
Date: Sun, 1 Sep 2019 17:47:37 +0200 [thread overview]
Message-ID: <896e5738996b0cf2a7b8670c68610b5c45b31877.1567326213.git.noring@nocrew.org> (raw)
In-Reply-To: <cover.1567326213.git.noring@nocrew.org>
The DMA controller handles transfers between main memory and peripheral
devices or the scratch-pad RAM (SPR)[1].
References:
[1] "EE User's Manual", version 6.0, Sony Computer Entertainment Inc.,
pp. 23-24, 41-80.
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
arch/mips/include/asm/mach-ps2/dmac.h | 189 ++++++++++++++++++++++++++
1 file changed, 189 insertions(+)
create mode 100644 arch/mips/include/asm/mach-ps2/dmac.h
diff --git a/arch/mips/include/asm/mach-ps2/dmac.h b/arch/mips/include/asm/mach-ps2/dmac.h
new file mode 100644
index 000000000000..30a0f72eeab3
--- /dev/null
+++ b/arch/mips/include/asm/mach-ps2/dmac.h
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PlayStation 2 DMA controller (DMAC)
+ *
+ * Copyright (C) 2019 Fredrik Noring
+ */
+
+/**
+ * DOC:
+ *
+ * The DMA controller handles transfers between main memory and peripheral
+ * devices or the scratch-pad RAM (SPR).
+ *
+ * The DMAC arbitrates the main bus at the same time, and supports chain
+ * mode which switches transfer addresses according to DMA tags attached to
+ * the transfer. The stall control synchronises two-channel transfers with
+ * priority control.
+ *
+ * Data is transferred in 128-bit words that must be aligned. Bus snooping
+ * is not performed.
+ */
+
+#ifndef __ASM_MACH_PS2_DMAC_H
+#define __ASM_MACH_PS2_DMAC_H
+
+#include <asm/types.h>
+
+/* Channel 0: Vector core operation unit 0 (VU0) interface (VIF0) */
+#define DMAC_VIF0_CHCR 0x10008000 /* VIF0 channel control */
+#define DMAC_VIF0_MADR 0x10008010 /* VIF0 memory address */
+#define DMAC_VIF0_QWC 0x10008020 /* VIF0 quadword count */
+#define DMAC_VIF0_TADR 0x10008030 /* VIF0 tag address */
+#define DMAC_VIF0_ASR0 0x10008040 /* VIF0 address stack 0 */
+#define DMAC_VIF0_ASR1 0x10008050 /* VIF0 address stack 1 */
+
+/* Channel 1: Vector core operation unit 1 (VU1) interface (VIF1) */
+#define DMAC_VIF1_CHCR 0x10009000 /* VIF1 channel control */
+#define DMAC_VIF1_MADR 0x10009010 /* VIF1 memory address */
+#define DMAC_VIF1_QWC 0x10009020 /* VIF1 quadword count */
+#define DMAC_VIF1_TADR 0x10009030 /* VIF1 tag address */
+#define DMAC_VIF1_ASR0 0x10009040 /* VIF1 address stack 0 */
+#define DMAC_VIF1_ASR1 0x10009050 /* VIF1 address stack 1 */
+
+/* Channel 2: Graphics Synthesizer interface (GIF) */
+#define DMAC_GIF_CHCR 0x1000a000 /* GIF channel control */
+#define DMAC_GIF_MADR 0x1000a010 /* GIF memory address */
+#define DMAC_GIF_QWC 0x1000a020 /* GIF quadword count */
+#define DMAC_GIF_TADR 0x1000a030 /* GIF tag address */
+#define DMAC_GIF_ASR0 0x1000a040 /* GIF address stack 0 */
+#define DMAC_GIF_ASR1 0x1000a050 /* GIF address stack 1 */
+
+/* Channel 3: From image processor unit (IPU) */
+#define DMAC_FIPU_CHCR 0x1000b000 /* From IPU channel control */
+#define DMAC_FIPU_MADR 0x1000b010 /* From IPU memory address */
+#define DMAC_FIPU_QWC 0x1000b020 /* From IPU quadword count */
+
+/* Channel 4: To image processor unit (IPU) */
+#define DMAC_TIPU_CHCR 0x1000b400 /* To IPU channel control */
+#define DMAC_TIPU_MADR 0x1000b410 /* To IPU memory address */
+#define DMAC_TIPU_QWC 0x1000b420 /* To IPU quadword count */
+#define DMAC_TIPU_TADR 0x1000b430 /* To IPU tag address */
+
+/* Channel 5: Sub-system interface 0 (SIF0) */
+#define DMAC_SIF0_CHCR 0x1000c000 /* SIF0 channel control */
+#define DMAC_SIF0_MADR 0x1000c010 /* SIF0 memory address */
+#define DMAC_SIF0_QWC 0x1000c020 /* SIF0 quadword count */
+
+/* Channel 6: Sub-system interface 1 (SIF1) */
+#define DMAC_SIF1_CHCR 0x1000c400 /* SIF1 channel control */
+#define DMAC_SIF1_MADR 0x1000c410 /* SIF1 memory address */
+#define DMAC_SIF1_QWC 0x1000c420 /* SIF1 quadword count */
+#define DMAC_SIF1_TADR 0x1000c430 /* SIF1 tag address */
+
+/* Channel 7: Sub-system interface 2 (SIF2) */
+#define DMAC_SIF2_CHCR 0x1000c800 /* SIF2 channel control */
+#define DMAC_SIF2_MADR 0x1000c810 /* SIF2 memory address */
+#define DMAC_SIF2_QWC 0x1000c820 /* SIF2 quadword count */
+
+/* Channel 8: From scratch-pad RAM (SPR) */
+#define DMAC_FSPR_CHCR 0x1000d000 /* From SPR channel control */
+#define DMAC_FSPR_MADR 0x1000d010 /* From SPR memory address */
+#define DMAC_FSPR_QWC 0x1000d020 /* From SPR quadword count */
+#define DMAC_FSPR_SADR 0x1000d080 /* From SPR address */
+
+/* Channel 9: To scratch-pad RAM (SPR) */
+#define DMAC_TSPR_CHCR 0x1000d400 /* To SPR channel control */
+#define DMAC_TSPR_MADR 0x1000d410 /* To SPR memory address */
+#define DMAC_TSPR_QWC 0x1000d420 /* To SPR quadword count */
+#define DMAC_TSPR_TADR 0x1000d430 /* To SPR tag address */
+#define DMAC_TSPR_SADR 0x1000d480 /* To SPR address */
+
+#define DMAC_CHCR_DIR_TOMEM (0 << 0) /* Direction to memory */
+#define DMAC_CHCR_DIR_FROMMEM (1 << 0) /* Direction from memory */
+#define DMAC_CHCR_MOD_NORMAL (0 << 2) /* Mode normal */
+#define DMAC_CHCR_MOD_CHAIN (1 << 2) /* Mode chain */
+#define DMAC_CHCR_MOD_ILEAVE (2 << 2) /* Mode interleave */
+#define DMAC_CHCR_ASP_NONE (0 << 4) /* 0 address stack pointer */
+#define DMAC_CHCR_ASP_1ADDR (1 << 4) /* 1 address stack pointer */
+#define DMAC_CHCR_ASP_2ADDR (2 << 4) /* 2 address stack pointer */
+#define DMAC_CHCR_TTE_OFF (0 << 6) /* Tag transfer enable off */
+#define DMAC_CHCR_TTE_ON (1 << 6) /* Tag transfer enable on */
+#define DMAC_CHCR_TIE_OFF (0 << 7) /* Tag interrupt enable off */
+#define DMAC_CHCR_TIE_ON (1 << 7) /* Tag interrupt enable on */
+#define DMAC_CHCR_STR_STOP (0 << 8) /* Stop DMA */
+#define DMAC_CHCR_STR_START (1 << 8) /* Start DMA */
+
+#define DMAC_CHCR_STOP DMAC_CHCR_STR_STOP
+#define DMAC_CHCR_BUSY DMAC_CHCR_STR_START
+#define DMAC_CHCR_SENDN (DMAC_CHCR_DIR_FROMMEM | \
+ DMAC_CHCR_MOD_NORMAL | \
+ DMAC_CHCR_ASP_NONE | \
+ DMAC_CHCR_TTE_OFF | \
+ DMAC_CHCR_TIE_OFF | \
+ DMAC_CHCR_STR_START)
+#define DMAC_CHCR_SENDN_TIE (DMAC_CHCR_DIR_FROMMEM | \
+ DMAC_CHCR_MOD_NORMAL | \
+ DMAC_CHCR_ASP_NONE | \
+ DMAC_CHCR_TTE_OFF | \
+ DMAC_CHCR_TIE_ON | \
+ DMAC_CHCR_STR_START)
+#define DMAC_CHCR_SENDC (DMAC_CHCR_DIR_FROMMEM | \
+ DMAC_CHCR_MOD_CHAIN | \
+ DMAC_CHCR_ASP_NONE | \
+ DMAC_CHCR_TTE_OFF | \
+ DMAC_CHCR_TIE_OFF | \
+ DMAC_CHCR_STR_START)
+#define DMAC_CHCR_SENDC_TTE (DMAC_CHCR_DIR_FROMMEM | \
+ DMAC_CHCR_MOD_CHAIN | \
+ DMAC_CHCR_ASP_NONE | \
+ DMAC_CHCR_TTE_ON | \
+ DMAC_CHCR_TIE_OFF | \
+ DMAC_CHCR_STR_START)
+#define DMAC_CHCR_RECVN (DMAC_CHCR_DIR_TOMEM | \
+ DMAC_CHCR_MOD_NORMAL | \
+ DMAC_CHCR_ASP_NONE | \
+ DMAC_CHCR_TTE_OFF | \
+ DMAC_CHCR_TIE_OFF | \
+ DMAC_CHCR_STR_START)
+#define DMAC_CHCR_RECVC_TIE (DMAC_CHCR_DIR_TOMEM | \
+ DMAC_CHCR_MOD_CHAIN | \
+ DMAC_CHCR_ASP_NONE | \
+ DMAC_CHCR_TTE_OFF | \
+ DMAC_CHCR_TIE_ON | \
+ DMAC_CHCR_STR_START)
+
+#define DMAC_CTRL 0x1000e000 /* DMAC control */
+#define DMAC_STAT 0x1000e010 /* DMAC status */
+#define DMAC_PCR 0x1000e020 /* DMAC priority control */
+#define DMAC_SQWC 0x1000e030 /* DMAC skip quadword */
+#define DMAC_RBSR 0x1000e040 /* DMAC ring buffer size */
+#define DMAC_RBOR 0x1000e050 /* DMAC ring buffer offset */
+#define DMAC_STADR 0x1000e060 /* DMAC stall address */
+
+/*
+ * The lower 16 bits are status bits and the upper 16 bits are mask bits.
+ * Status bit cleared by writing 1. Mask bits are reversed by writing 1.
+ */
+#define DMAC_STAT_MASK 0x1000e010
+
+#define DMAC_STAT_VIF0S (1 << 0) /* Ch0 interrupt status VIF0 */
+#define DMAC_STAT_VIF1S (1 << 1) /* Ch1 interrupt status VIF1 */
+#define DMAC_STAT_GIFS (1 << 2) /* Ch2 interrupt status GIF */
+#define DMAC_STAT_FIPUS (1 << 3) /* Ch3 interrupt status from IPU */
+#define DMAC_STAT_TIPUS (1 << 4) /* Ch4 interrupt status to IPU */
+#define DMAC_STAT_SIF0S (1 << 5) /* Ch5 interrupt status SIF0 */
+#define DMAC_STAT_SIF1S (1 << 6) /* Ch6 interrupt status SIF1 */
+#define DMAC_STAT_SIF2S (1 << 7) /* Ch7 interrupt status SIF2 */
+#define DMAC_STAT_FSPRS (1 << 8) /* Ch8 interrupt status from SPR */
+#define DMAC_STAT_TSPRS (1 << 9) /* Ch9 interrupt status to SPR */
+#define DMAC_STAT_SIS (1 << 13) /* DMA stall interrupt status */
+#define DMAC_STAT_MEIS (1 << 14) /* MFIFO empty interrupt status */
+#define DMAC_STAT_BEIS (1 << 15) /* BUSERR interrupt status */
+#define DMAC_STAT_VIF0M (1 << 16) /* Ch0 interrupt mask VIF0 */
+#define DMAC_STAT_VIF1M (1 << 17) /* Ch1 interrupt mask VIF1 */
+#define DMAC_STAT_GIFM (1 << 18) /* Ch2 interrupt mask GIF */
+#define DMAC_STAT_FIPUM (1 << 19) /* Ch3 interrupt mask from IPU */
+#define DMAC_STAT_TIPUM (1 << 20) /* Ch4 interrupt mask to IPU */
+#define DMAC_STAT_SIF0M (1 << 21) /* Ch5 interrupt mask SIF0 */
+#define DMAC_STAT_SIF1M (1 << 22) /* Ch6 interrupt mask SIF1 */
+#define DMAC_STAT_SIF2M (1 << 23) /* Ch7 interrupt mask SIF2 */
+#define DMAC_STAT_FSPRM (1 << 24) /* Ch8 interrupt mask from SPR */
+#define DMAC_STAT_TSPRM (1 << 25) /* Ch9 interrupt mask to SPR */
+#define DMAC_STAT_SIM (1 << 29) /* DMA stall interrupt mask */
+#define DMAC_STAT_MEIM (1 << 30) /* MFIFO empty interrupt mask */
+
+#define DMAC_ENABLER 0x1000f520 /* Acquisition of DMA suspend status */
+#define DMAC_ENABLEW 0x1000f590 /* DMA suspend control */
+
+#endif /* __ASM_MACH_PS2_DMAC_H */
--
2.21.0
next prev parent reply other threads:[~2019-09-01 15:47 UTC|newest]
Thread overview: 162+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-01 15:35 [PATCH 000/120] Linux for the PlayStation 2 Fredrik Noring
2019-09-01 15:35 ` [PATCH 001/120] MIPS: R5900: Initial support for the Emotion Engine in " Fredrik Noring
2019-09-01 21:14 ` Maciej W. Rozycki
2019-09-02 15:09 ` Fredrik Noring
2019-09-01 15:36 ` [PATCH 002/120] MIPS: R5900: Trap the RDHWR instruction as an SQ address exception Fredrik Noring
2019-09-01 22:00 ` Maciej W. Rozycki
2020-11-19 7:15 ` Philippe Mathieu-Daudé
2020-11-19 13:28 ` Maciej W. Rozycki
2020-11-19 13:42 ` Maciej W. Rozycki
2020-12-12 10:58 ` Fredrik Noring
2020-12-12 11:36 ` Maciej W. Rozycki
2020-12-12 12:14 ` Fredrik Noring
2020-12-13 11:43 ` Fredrik Noring
2019-09-01 15:36 ` [PATCH 003/120] MIPS: R5900: Sign-extend o32 system call registers Fredrik Noring
2019-09-01 15:37 ` [PATCH 004/120] MIPS: R5900: Reset bits 127..64 of GPRs in RESTORE_SOME Fredrik Noring
2019-09-01 15:38 ` [PATCH 005/120] MIPS: R5900: Reset the funnel shift amount (SA) register " Fredrik Noring
2019-09-01 15:38 ` [PATCH 006/120] MIPS: R5900: Workaround for the short loop bug Fredrik Noring
2019-09-01 15:39 ` [PATCH 007/120] MIPS: R5900: Add the SYNC.P instruction Fredrik Noring
2019-09-01 15:39 ` [PATCH 008/120] MIPS: R5900: Add implicit SYNC.P to the UASM_i_M[FT]C0 macros Fredrik Noring
2019-09-01 15:39 ` [PATCH 009/120] MIPS: R5900: Add mandatory SYNC.P to all M[FT]C0 instructions Fredrik Noring
2019-09-01 15:39 ` [PATCH 010/120] MIPS: R5900: Workaround exception NOP execution bug (FLX05) Fredrik Noring
2019-09-01 23:01 ` Philippe Mathieu-Daudé
2019-09-01 15:40 ` [PATCH 011/120] MIPS: R5900: Avoid pipeline hazard with the TLBP instruction Fredrik Noring
2019-09-01 17:15 ` Sergei Shtylyov
2019-09-01 17:36 ` Fredrik Noring
2019-09-01 15:40 ` [PATCH 012/120] MIPS: R5900: Avoid pipeline hazards with the TLBW[IR] instructions Fredrik Noring
2019-09-01 15:40 ` [PATCH 013/120] MIPS: R5900: Avoid pipeline hazard with the TLBR instruction Fredrik Noring
2019-09-01 15:41 ` [PATCH 014/120] MIPS: R5900: Install final length of TLB refill handler rather than 256 bytes Fredrik Noring
2019-09-01 15:41 ` [PATCH 015/120] MIPS: R5900: Verify that the TLB refill handler does not overflow Fredrik Noring
2019-09-01 15:41 ` [PATCH 016/120] MIPS: R5900: The ERET instruction has issues with delay slot and CACHE Fredrik Noring
2019-09-01 15:42 ` [PATCH 017/120] MIPS: R5900: Define CACHE instruction operation field encodings Fredrik Noring
2019-09-01 15:42 ` [PATCH 018/120] MIPS: R5900: Workaround where MSB must be 0 for the instruction cache Fredrik Noring
2019-09-01 15:42 ` [PATCH 019/120] MIPS: R5900: Use SYNC.L for data cache and SYNC.P for " Fredrik Noring
2019-09-01 15:43 ` [PATCH 020/120] MIPS: R5900: Define CP0.Config register fields Fredrik Noring
2019-09-01 23:04 ` Philippe Mathieu-Daudé
2019-09-01 15:43 ` [PATCH 021/120] MIPS: R5900: Workaround for CACHE instruction near branch delay slot Fredrik Noring
2019-09-01 15:46 ` [PATCH 022/120] MIPS: R5900: Support 64-bit inq() and outq() macros in 32-bit kernels Fredrik Noring
2019-09-04 1:04 ` Jiaxun Yang
2019-09-04 16:00 ` Maciej W. Rozycki
2019-09-01 15:46 ` [PATCH 023/120] MIPS: R5900: Add MFSA and MTSA instructions for the special SA register Fredrik Noring
2019-09-01 15:46 ` [PATCH 024/120] MIPS: PS2: Define PlayStation 2 I/O port, ROM and RAM address spaces Fredrik Noring
2019-09-01 15:47 ` [PATCH 025/120] MIPS: PS2: Define interrupt controller, DMA and timer IRQs Fredrik Noring
2019-09-01 15:47 ` [PATCH 026/120] MIPS: PS2: Interrupt controller (INTC) IRQ support Fredrik Noring
2019-09-01 15:47 ` Fredrik Noring [this message]
2019-09-01 15:47 ` [PATCH 028/120] MIPS: PS2: DMAC: Define tag structures Fredrik Noring
2019-09-01 15:48 ` [PATCH 029/120] MIPS: PS2: DMAC: IRQ support Fredrik Noring
2019-09-01 15:48 ` [PATCH 030/120] MIPS: PS2: Timer support Fredrik Noring
2019-09-01 15:48 ` [PATCH 031/120] MIPS: PS2: SCMD: System command support Fredrik Noring
2019-09-01 15:48 ` [PATCH 032/120] MIPS: PS2: SCMD: System power off command Fredrik Noring
2019-09-01 15:48 ` [PATCH 033/120] MIPS: PS2: SCMD: Read system machine name command Fredrik Noring
2019-09-01 15:49 ` [PATCH 034/120] MIPS: PS2: SCMD: Read system command for the real-time clock (RTC) Fredrik Noring
2019-09-01 15:49 ` [PATCH 035/120] MIPS: PS2: SCMD: Set " Fredrik Noring
2019-09-01 15:49 ` [PATCH 036/120] MIPS: PS2: ROM: Iterate over the files in a given ROM directory Fredrik Noring
2019-09-01 15:49 ` [PATCH 037/120] MIPS: PS2: ROM: Find ROM files with a given name, if they exist Fredrik Noring
2019-09-01 15:50 ` [PATCH 038/120] MIPS: PS2: ROM: Read data for a given ROM file name Fredrik Noring
2019-09-02 9:05 ` Sergei Shtylyov
2019-09-04 11:46 ` Sergei Shtylyov
2019-09-06 13:07 ` Fredrik Noring
2019-09-01 15:50 ` [PATCH 039/120] MIPS: PS2: ROM: Read extended information for a given ROM file Fredrik Noring
2019-09-01 15:50 ` [PATCH 040/120] MIPS: PS2: ROM: Read and decode the ROMVER file Fredrik Noring
2019-09-01 15:52 ` [PATCH 041/120] MIPS: PS2: ROM: Resolve the name for the type in " Fredrik Noring
2019-09-01 15:52 ` [PATCH 042/120] MIPS: PS2: ROM: Resolve the name for the region " Fredrik Noring
2019-09-01 15:53 ` [PATCH 043/120] MIPS: PS2: ROM: Permit /dev/mem to access read-only memory Fredrik Noring
2019-09-01 15:53 ` [PATCH 044/120] MIPS: PS2: ROM: Sysfs module to inspect ROM files Fredrik Noring
2019-09-01 15:54 ` [PATCH 045/120] MIPS: PS2: ROM: Provide extended file information via sysfs Fredrik Noring
2019-09-01 15:54 ` [PATCH 046/120] MIPS: PS2: Identify the machine by model name Fredrik Noring
2019-09-01 15:54 ` [PATCH 047/120] MIPS: PS2: Let the system type be Sony PlayStation 2 Fredrik Noring
2019-09-01 23:09 ` Philippe Mathieu-Daudé
2019-09-01 15:55 ` [PATCH 048/120] MIPS: Define and use cpu_relax_forever() for various halting loops Fredrik Noring
2019-09-01 15:55 ` [PATCH 049/120] MIPS: PS2: Power off support Fredrik Noring
2019-09-01 15:55 ` [PATCH 050/120] MIPS: PS2: Real-time clock (RTC) driver Fredrik Noring
2019-09-01 15:56 ` [PATCH 051/120] MIPS: PS2: IOP: I/O processor DMA register PCR2 set and clear Fredrik Noring
2019-09-01 15:57 ` [PATCH 052/120] MIPS: PS2: SIF: Sub-system interface reset of the I/O processor (IOP) Fredrik Noring
2019-09-01 15:57 ` [PATCH 053/120] MIPS: PS2: IOP: Define error numbers, descriptions and errno mapping Fredrik Noring
2019-09-01 15:58 ` [PATCH 054/120] MIPS: PS2: SIF: SIF register write command support Fredrik Noring
2019-09-01 15:58 ` [PATCH 055/120] MIPS: PS2: SIF: Respond to remote procedure call (RPC) bind command Fredrik Noring
2019-09-01 15:58 ` [PATCH 056/120] MIPS: PS2: SIF: Respond to RPC bind end command Fredrik Noring
2019-09-01 15:59 ` [PATCH 057/120] MIPS: PS2: SIF: Reset the SIF0 (sub-to-main) DMA controller Fredrik Noring
2019-09-01 15:59 ` [PATCH 058/120] MIPS: PS2: SIF: Handle SIF0 (sub-to-main) RPCs via interrupts Fredrik Noring
2019-09-01 15:59 ` [PATCH 059/120] MIPS: PS2: SIF: Enable the IOP to issue SIF commands Fredrik Noring
2019-09-01 16:00 ` [PATCH 060/120] MIPS: PS2: SIF: Enable the IOP to issue SIF RPCs Fredrik Noring
2019-09-01 16:01 ` [PATCH 061/120] MIPS: PS2: SIF: sif_rpc_bind() to request an RPC server connection Fredrik Noring
2019-09-01 16:02 ` [PATCH 062/120] MIPS: PS2: SIF: sif_rpc_unbind() to release " Fredrik Noring
2019-09-01 16:02 ` [PATCH 063/120] MIPS: PS2: SIF: sif_rpc() to issue a remote procedure call Fredrik Noring
2019-09-01 16:03 ` [PATCH 064/120] MIPS: PS2: IOP: Permit /dev/mem to access IOP memory Fredrik Noring
2019-09-01 16:03 ` [PATCH 065/120] MIPS: PS2: IOP: I/O processor memory support Fredrik Noring
2019-09-01 16:10 ` [PATCH 066/120] FIXME: Export _dma_cache_{wback,wback_inv,inv} Fredrik Noring
2019-09-01 16:10 ` [PATCH 067/120] MIPS: PS2: IOP: Module linking support Fredrik Noring
2019-09-01 16:11 ` [PATCH 068/120] MIPS: PS2: IOP: Verify that modules are IRX objects Fredrik Noring
2019-09-01 16:11 ` [PATCH 069/120] MIPS: PS2: IOP: Module version compatibility verification Fredrik Noring
2019-09-01 16:11 ` [PATCH 070/120] MIPS: PS2: IOP: Avoid linking already linked library modules Fredrik Noring
2019-09-01 16:12 ` [PATCH 071/120] MIPS: PS2: IOP: Resolve module dependencies Fredrik Noring
2019-09-01 16:12 ` [PATCH 072/120] MIPS: PS2: IOP: SIF printk command support Fredrik Noring
2019-09-01 17:44 ` Sergei Shtylyov
2019-09-01 18:08 ` Fredrik Noring
2019-09-01 16:16 ` [PATCH 073/120] MIPS: PS2: IOP: Heap memory allocate and free Fredrik Noring
2019-09-01 16:16 ` [PATCH 074/120] MIPS: PS2: SIF: Request RPC IRQ command Fredrik Noring
2019-09-01 16:17 ` [PATCH 075/120] MIPS: PS2: IOP: IRQ support Fredrik Noring
2019-09-01 16:17 ` [PATCH 076/120] MIPS: PS2: GS: Define privileged Graphics Synthesizer registers Fredrik Noring
2019-09-01 16:18 ` [PATCH 077/120] MIPS: PS2: GS: Write privileged registers Fredrik Noring
2019-09-01 16:18 ` [PATCH 078/120] MIPS: PS2: GS: Read " Fredrik Noring
2019-09-01 16:18 ` [PATCH 079/120] MIPS: PS2: GS: Define privileged register structures Fredrik Noring
2019-09-01 16:19 ` [PATCH 080/120] MIPS: PS2: GS: Define gs_xorq_imr() Fredrik Noring
2019-09-01 16:20 ` [PATCH 081/120] MIPS: PS2: GS: Privileged register write macros with named fields Fredrik Noring
2019-09-01 16:20 ` [PATCH 082/120] MIPS: PS2: GS: IRQ support Fredrik Noring
2019-09-01 16:21 ` [PATCH 083/120] MIPS: PS2: GS: Define Graphics Synthesizer primitive structures Fredrik Noring
2019-09-01 16:21 ` [PATCH 084/120] MIPS: PS2: GIF: Define Graphics Synthesizer interface structures Fredrik Noring
2019-09-01 16:22 ` [PATCH 085/120] MIPS: PS2: GIF: Graphics Synthesizer interface support Fredrik Noring
2019-09-01 16:22 ` [PATCH 086/120] MIPS: PS2: GS: Graphics Synthesizer device init and video clock Fredrik Noring
2019-09-01 16:23 ` [PATCH 087/120] MIPS: PS2: GS: Compute block count and indices Fredrik Noring
2019-09-01 16:23 ` [PATCH 088/120] MIPS: PS2: GS: Primitive and texel coordinate transformations Fredrik Noring
2019-09-01 16:23 ` [PATCH 089/120] MIPS: PS2: GS: Approximate video region with ROM region Fredrik Noring
2019-09-01 16:24 ` [PATCH 090/120] macro: Extend COUNT_ARGS() from 12 to 32 arguments Fredrik Noring
2019-09-01 16:25 ` [PATCH 091/120] MIPS: PS2: GS: Show privileged registers with sysfs Fredrik Noring
2019-09-01 16:25 ` [PATCH 092/120] MIPS: PS2: GS: Store " Fredrik Noring
2019-09-01 16:25 ` [PATCH 093/120] fbdev: Add fb_warn_once() variant that only prints a warning once Fredrik Noring
2019-09-01 23:12 ` Philippe Mathieu-Daudé
2019-09-01 16:26 ` [PATCH 094/120] MIPS: PS2: FB: Frame buffer driver for the PlayStation 2 Fredrik Noring
2019-09-02 1:12 ` Jiaxun Yang
2019-09-02 14:40 ` Fredrik Noring
2019-09-02 17:47 ` Aaro Koskinen
2019-09-03 14:32 ` Fredrik Noring
2019-09-03 4:01 ` Jiaxun Yang
2019-09-03 17:42 ` Fredrik Noring
2019-09-03 17:59 ` Maciej W. Rozycki
2019-09-03 18:46 ` Fredrik Noring
2020-12-13 13:20 ` Fredrik Noring
2022-01-29 11:23 ` Fredrik Noring
2022-01-29 11:23 ` Fredrik Noring
2019-09-01 16:30 ` [PATCH 095/120] MIPS: PS2: FB: fb_set_par() standard-definition television support Fredrik Noring
2019-09-01 16:30 ` [PATCH 096/120] MIPS: PS2: FB: fb_set_par() high-definition " Fredrik Noring
2019-09-01 16:31 ` [PATCH 097/120] MIPS: PS2: FB: fb_set_par() VESA computer display mode support Fredrik Noring
2019-09-01 16:31 ` [PATCH 098/120] MIPS: PS2: FB: Preconfigure standard PAL, NTSC and VESA display modes Fredrik Noring
2019-09-01 16:31 ` [PATCH 099/120] MIPS: PS2: FB: Reset the Graphics Synthesizer drawing environment Fredrik Noring
2019-09-01 16:32 ` [PATCH 100/120] MIPS: PS2: FB: Clear the display buffer when changing video modes Fredrik Noring
2019-09-01 16:32 ` [PATCH 101/120] MIPS: PS2: FB: fb_setcolreg() 256 colour pseudo palette support Fredrik Noring
2019-09-01 16:32 ` [PATCH 102/120] MIPS: PS2: FB: fb_settile() with font stored as palette indexed textures Fredrik Noring
2019-09-01 16:32 ` [PATCH 103/120] MIPS: PS2: FB: Hardware accelerated fb_tilecopy() support Fredrik Noring
2019-09-01 16:33 ` [PATCH 104/120] MIPS: PS2: FB: Hardware accelerated fb_tilefill() support Fredrik Noring
2019-09-01 16:33 ` [PATCH 105/120] MIPS: PS2: FB: Simplified fb_tileblit() support Fredrik Noring
2019-09-01 16:33 ` [PATCH 106/120] MIPS: PS2: FB: fb_tilecursor() placeholder Fredrik Noring
2019-09-01 16:33 ` [PATCH 107/120] MIPS: PS2: FB: Hardware accelerated fb_pan_display() support Fredrik Noring
2019-09-01 16:34 ` [PATCH 108/120] MIPS: PS2: FB: fb_blank() display power management signaling (DPMS) Fredrik Noring
2019-09-01 16:34 ` [PATCH 109/120] MIPS: PS2: FB: Disable GIF DMA completion interrupts Fredrik Noring
2019-09-01 16:34 ` [PATCH 110/120] MIPS: PS2: FB: PAL and NTSC grayscale support Fredrik Noring
2019-09-01 16:34 ` [PATCH 111/120] MIPS: PS2: FB: Analogue display mode adjustment module parameter Fredrik Noring
2019-09-01 16:35 ` [PATCH 112/120] USB: OHCI: Support for the PlayStation 2 Fredrik Noring
2019-09-01 16:35 ` [PATCH 113/120] USB: OHCI: OHCI_INTR_MIE workaround for freeze on " Fredrik Noring
2019-09-01 16:35 ` [PATCH 114/120] MIPS: PS2: Workaround for unexpected uLaunchELF CP0 Status user mode Fredrik Noring
2019-09-01 16:35 ` [PATCH 115/120] MIPS: PS2: Define initial PlayStation 2 devices Fredrik Noring
2019-09-01 16:35 ` [PATCH 116/120] MIPS: PS2: Define workarounds related to the PlayStation 2 Fredrik Noring
2019-09-01 16:36 ` [PATCH 117/120] MIPS: PS2: Define R5900 feature overrides Fredrik Noring
2019-09-01 16:36 ` [PATCH 118/120] MIPS: PS2: Define the PlayStation 2 platform Fredrik Noring
2019-09-01 16:36 ` [PATCH 119/120] MIPS: PS2: Initial support for the Sony PlayStation 2 Fredrik Noring
2019-09-01 16:37 ` [PATCH 120/120] MIPS: Fix name of BOOT_MEM_ROM_DATA Fredrik Noring
2019-09-01 23:15 ` Philippe Mathieu-Daudé
2019-09-02 1:02 ` Jiaxun Yang
2019-09-02 15:26 ` Fredrik Noring
2019-09-03 3:50 ` Jiaxun Yang
2019-09-03 16:06 ` Fredrik Noring
2019-09-04 14:19 ` [PATCH 000/120] Linux for the PlayStation 2 Paul Burton
2019-09-05 18:32 ` Fredrik Noring
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