Re: [PATCH] drm/i915: Fix offset page-flips on i965+

From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Fix offset page-flips on i965+
Date: Sun, 08 Aug 2010 12:39:00 +0100	[thread overview]
Message-ID: <89k83a$974h4e@azsmga001.ch.intel.com> (raw)
In-Reply-To: <1281259225-23421-1-git-send-email-chris@chris-wilson.co.uk>

On Sun,  8 Aug 2010 10:20:25 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>  		OUT_RING(MI_DISPLAY_FLIP |
>  			 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
> -		OUT_RING(fb->pitch);
> -		OUT_RING(offset | obj_priv->tiling_mode);
> -		pipesrc = I915_READ(pipesrc_reg); 
> -		OUT_RING(pipesrc & 0x0fff0fff);
> +		OUT_RING(fb->pitch | obj_priv->tiling_mode);
> +		/* i965+ uses the linear or tiled offsets from the
> +		 * Display Registers (which do not change across a page-flip)
> +		 * so we need only reprogram the base address.
> +		 */
> +		OUT_RING(obj_priv->gtt_offset);

There's a discrepancy here between our internal docs and the publish PDFs
for MI_DISPLAY_FLIP. In our docs, we have pitch | tiling. In the
PDF, it's address | tiling. There are other inconsistencies in the
bitfields surround this in the PDF, so it is worth a second set of eyes
checking this.

-- 
Chris Wilson, Intel Open Source Technology Centre