RE: Use rsvd_bits_mask in load_pdptrs for cleanup and considing EXB bit

From: "Dong, Eddie" <eddie.dong@intel.com>
To: Avi Kivity <avi@redhat.com>
Cc: "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	"Dong, Eddie" <eddie.dong@intel.com>
Subject: RE: Use rsvd_bits_mask in load_pdptrs for cleanup and considing EXB bit
Date: Mon, 30 Mar 2009 21:46:56 +0800	[thread overview]
Message-ID: <9832F13BD22FB94A829F798DA4A8280501A3C02403@pdsmsx503.ccr.corp.intel.com> (raw)
In-Reply-To: <49D0B76D.3080304@redhat.com>

Avi Kivity wrote:
> Dong, Eddie wrote:
>> @@ -2199,6 +2194,9 @@ void reset_rsvds_bits_mask(struct kvm_vcpu
>>  		*vcpu, int level) context->rsvd_bits_mask[1][0] = 0;
>>  		break;
>>  	case PT32E_ROOT_LEVEL:
>> +		context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
>> +			rsvd_bits(maxphyaddr, 62) |
>> +			rsvd_bits(7, 8) | rsvd_bits(1, 2);	/* PDPTE */
>>  		context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
>>  			rsvd_bits(maxphyaddr, 62);		/* PDE */
>>  		context->rsvd_bits_mask[0][0] = exb_bit_rsvd
> 
> Are you sure that PDPTEs support NX?  They don't support R/W and U/S,
> so it seems likely that NX is reserved as well even when EFER.NXE is
> enabled. 

I am refering Fig 3-20/3-21 of SDM3A, but I think Fig3-20/21 has EXB bit missed since Table 3-5 and section 3.10.3.
I will double check with internal architect. 
thx, eddie