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From: Tom Rix <trix@redhat.com>
To: "Wu, Hao" <hao.wu@intel.com>, "Xu, Yilun" <yilun.xu@intel.com>,
	"mdf@kernel.org" <mdf@kernel.org>,
	"linux-fpga@vger.kernel.org" <linux-fpga@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: "bhu@redhat.com" <bhu@redhat.com>
Subject: Re: [PATCH 1/2] fpga: dfl: pci: reduce the scope of variable 'ret'
Date: Thu, 16 Apr 2020 09:56:47 -0700	[thread overview]
Message-ID: <9b1d85e0-4f44-179b-c847-af858fcc212a@redhat.com> (raw)
In-Reply-To: <DM6PR11MB3819619E9B2C7326218247E385D80@DM6PR11MB3819.namprd11.prod.outlook.com>

Please check the scope.

On linus/master, the result of this change looks like

static int cci_pci_sriov_configure(struct pci_dev *pcidev, int num_vfs)
{
    struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
    struct dfl_fpga_cdev *cdev = drvdata->cdev;

    if (!num_vfs) {
        /*
         * disable SRIOV and then put released ports back to default
         * PF access mode.
         */
        pci_disable_sriov(pcidev);

        dfl_fpga_cdev_config_ports_pf(cdev);

    } else {
        int ret; <--- defined here

        /*
         * before enable SRIOV, put released ports into VF access mode
         * first of all.
         */
        ret = dfl_fpga_cdev_config_ports_vf(cdev, num_vfs);
        if (ret)
            return ret;

        ret = pci_enable_sriov(pcidev, num_vfs);
        if (ret)
            dfl_fpga_cdev_config_ports_pf(cdev);
    }

    return ret;  <---- not in scope, not defined here
}

Tom


  reply	other threads:[~2020-04-16 16:57 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-16  3:11 [PATCH 0/2] Bug fixes for FPGA DFL Xu Yilun
2020-04-16  3:11 ` [PATCH 1/2] fpga: dfl: pci: reduce the scope of variable 'ret' Xu Yilun
2020-04-16  8:04   ` Wu, Hao
2020-04-16  8:04     ` Wu, Hao
2020-04-16 16:56     ` Tom Rix [this message]
2020-04-17  1:56       ` Xu Yilun
2020-04-17  1:56         ` Xu Yilun
2020-04-17  3:05         ` Wu, Hao
2020-04-17  3:21           ` Xu Yilun
2020-04-17  5:55             ` Wu, Hao
2020-04-16  3:11 ` [PATCH 2/2] fpga: dfl: fix bug in port reset handshake Xu Yilun
2020-04-16  8:06   ` Wu, Hao
2020-04-16  8:06     ` Wu, Hao

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