From: "Tian, Kevin" <kevin.tian@intel.com>
To: Jacob Pan <jacob.jun.pan@linux.intel.com>,
LKML <linux-kernel@vger.kernel.org>,
"iommu@lists.linux.dev" <iommu@lists.linux.dev>,
Lu Baolu <baolu.lu@linux.intel.com>,
Joerg Roedel <joro@8bytes.org>
Cc: Robin Murphy <robin.murphy@arm.com>,
Will Deacon <will@kernel.org>,
"David Woodhouse" <dwmw2@infradead.org>,
"Raj, Ashok" <ashok.raj@intel.com>,
"Liu, Yi L" <yi.l.liu@intel.com>,
"stable@vger.kernel.org" <stable@vger.kernel.org>,
"Ghorai, Sukumar" <sukumar.ghorai@intel.com>
Subject: RE: [PATCH v4] iommu/vt-d: Fix PASID directory pointer coherency
Date: Fri, 10 Feb 2023 01:30:35 +0000 [thread overview]
Message-ID: <BN9PR11MB52766B2EBACFEC8DE3CE4A9C8CDE9@BN9PR11MB5276.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20230209212843.1788125-1-jacob.jun.pan@linux.intel.com>
> From: Jacob Pan <jacob.jun.pan@linux.intel.com>
> Sent: Friday, February 10, 2023 5:29 AM
>
> On platforms that do not support IOMMU Extended capability bit 0
> Page-walk Coherency, CPU caches are not snooped when IOMMU is
> accessing
> any translation structures. IOMMU access goes only directly to
> memory. Intel IOMMU code was missing a flush for the PASID table
> directory that resulted in the unrecoverable fault as shown below.
>
> This patch adds clflush calls whenever allocating and updating
> a PASID table directory to ensure cache coherency.
>
> On the reverse direction, there's no need to clflush the PASID directory
> pointer when we deactivate a context entry in that IOMMU hardware will
> not see the old PASID directory pointer after we clear the context entry.
> PASID directory entries are also never freed once allocated.
>
> [ 0.555386] DMAR: DRHD: handling fault status reg 3
> [ 0.555805] DMAR: [DMA Read NO_PASID] Request device [00:0d.2] fault
> addr 0x1026a4000 [fault reason 0x51] SM: Present bit in Directory Entry is
> clear
> [ 0.556348] DMAR: Dump dmar1 table entries for IOVA 0x1026a4000
> [ 0.556348] DMAR: scalable mode root entry: hi 0x0000000102448001, low
> 0x0000000101b3e001
> [ 0.556348] DMAR: context entry: hi 0x0000000000000000, low
> 0x0000000101b4d401
> [ 0.556348] DMAR: pasid dir entry: 0x0000000101b4e001
> [ 0.556348] DMAR: pasid table entry[0]: 0x0000000000000109
> [ 0.556348] DMAR: pasid table entry[1]: 0x0000000000000001
> [ 0.556348] DMAR: pasid table entry[2]: 0x0000000000000000
> [ 0.556348] DMAR: pasid table entry[3]: 0x0000000000000000
> [ 0.556348] DMAR: pasid table entry[4]: 0x0000000000000000
> [ 0.556348] DMAR: pasid table entry[5]: 0x0000000000000000
> [ 0.556348] DMAR: pasid table entry[6]: 0x0000000000000000
> [ 0.556348] DMAR: pasid table entry[7]: 0x0000000000000000
> [ 0.556348] DMAR: PTE not present at level 4
>
> Cc: <stable@vger.kernel.org>
> Fixes: 0bbeb01a4faf ("iommu/vt-d: Manage scalalble mode PASID tables")
> Reported-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
> Signed-off-by: Ashok Raj <ashok.raj@intel.com>
> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
prev parent reply other threads:[~2023-02-10 1:30 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-09 21:28 [PATCH v4] iommu/vt-d: Fix PASID directory pointer coherency Jacob Pan
2023-02-10 1:30 ` Tian, Kevin [this message]
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