From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: Sergei Shtylyov <sergei.shtylyov@gmail.com>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Rob Herring <robh+dt@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Magnus Damm <magnus.damm@gmail.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>, LKML <linux-kernel@vger.kernel.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
linux-clk <linux-clk@vger.kernel.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v2 5/5] arm64: dts: renesas: rzg2l-smarc: Add scif0 pins
Date: Tue, 13 Jul 2021 15:34:26 +0100 [thread overview]
Message-ID: <CA+V-a8uB-QmtYjBQ7sondsfeQvBOMhmsYPd=0R4TrxzvO=zs6w@mail.gmail.com> (raw)
In-Reply-To: <53e6c8fa-311f-f100-dd06-d806ab593488@gmail.com>
Hi Sergei,
Thank you for the review.
On Tue, Jul 13, 2021 at 12:18 PM Sergei Shtylyov
<sergei.shtylyov@gmail.com> wrote:
>
> On 12.07.2021 22:44, Lad Prabhakar wrote:
>
> > Add scif0 pins in pinctrl node and update the scif0 node
> > to include pinctrl property.
>
> Properties? There are a couple... :-)
>
Agreed will update the commit message.
Cheers,
Prabhakar
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
> > index adcd4f50519e..0987163f25ee 100644
> > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
> [...]
> > clock-frequency = <24000000>;
> > };
> >
> > +&pinctrl {
> > + scif0_pins: scif0 {
> > + pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
> > + <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
> > + };
> > +};
> > +
> > &scif0 {
> > + pinctrl-0 = <&scif0_pins>;
> > + pinctrl-names = "default";
> > status = "okay";
> > };
> >
>
> MBR, Sergei
prev parent reply other threads:[~2021-07-13 14:35 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-12 19:44 [PATCH v2 0/5] pin and gpio controller driver for Renesas RZ/G2L Lad Prabhakar
2021-07-12 19:44 ` [PATCH v2 1/5] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Add DT bindings for RZ/G2L pinctrl Lad Prabhakar
2021-07-13 21:37 ` Rob Herring
2021-07-20 13:42 ` Geert Uytterhoeven
2021-07-30 12:36 ` Linus Walleij
2021-07-12 19:44 ` [PATCH v2 2/5] pinctrl: renesas: Add RZ/G2L pin and gpio controller driver Lad Prabhakar
2021-07-20 14:56 ` Geert Uytterhoeven
2021-07-21 13:07 ` Lad, Prabhakar
2021-07-12 19:44 ` [PATCH v2 3/5] drivers: clk: renesas: r9a07g044-cpg: Add GPIO clock and reset entries Lad Prabhakar
2021-07-13 13:37 ` Geert Uytterhoeven
2021-07-12 19:44 ` [PATCH v2 4/5] arm64: dts: renesas: r9a07g044: Add pinctrl node Lad Prabhakar
2021-07-12 19:44 ` [PATCH v2 5/5] arm64: dts: renesas: rzg2l-smarc: Add scif0 pins Lad Prabhakar
2021-07-13 11:18 ` Sergei Shtylyov
2021-07-13 14:34 ` Lad, Prabhakar [this message]
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