From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Linus Walleij <linus.walleij@linaro.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 1/4] pinctrl: renesas: r8a77990: Add QSPI[01] pins, groups and functions
Date: Fri, 20 Nov 2020 09:39:09 +0000 [thread overview]
Message-ID: <CA+V-a8uNsb3RGnNx8w3amhJCpOKk2df==9CbYPuermmUJM0y_w@mail.gmail.com> (raw)
In-Reply-To: <CAMuHMdUGqkqZVY9YZ1Xo=uq_4kn3ybh50VMSNBCLOSKWyDd3kw@mail.gmail.com>
Hi Geert,
Thank you for the review.
On Fri, Nov 20, 2020 at 9:20 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> On Thu, Nov 19, 2020 at 2:09 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > Add pins, groups and functions for QSPIO[01].
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will queue in renesas-pinctrl-for-v5.11...
>
> > --- a/drivers/pinctrl/renesas/pfc-r8a77990.c
> > +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
> > @@ -2810,6 +2810,57 @@ static const unsigned int pwm6_b_mux[] = {
> > PWM6_B_MARK,
> > };
> >
> > +/* - QSPI0 ------------------------------------------------------------------ */
> > +static const unsigned int qspi0_ctrl_pins[] = {
> > + /* SPCLK, SSL */
>
> ... with the missing QSPI0_ prefix added...
>
Argh missed that.
> > + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 5),
> > +};
> > +static const unsigned int qspi0_ctrl_mux[] = {
> > + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
> > +};
> > +static const unsigned int qspi0_data2_pins[] = {
> > + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
> > + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
> > +};
> > +static const unsigned int qspi0_data2_mux[] = {
> > + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
> > +};
> > +static const unsigned int qspi0_data4_pins[] = {
> > + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
> > + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
> > + /* QSPI0_IO2, QSPI0_IO3 */
>
> ... and the bogus space dropped.
>
Thanks for taking care of it.
Cheers,
Prabhakar
> > + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
> > +};
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
next prev parent reply other threads:[~2020-11-20 9:40 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-19 13:09 [PATCH 0/4] Renesas add QSPI{0,1} pins to r8a77{96,951,965,990} SoC Lad Prabhakar
2020-11-19 13:09 ` [PATCH 1/4] pinctrl: renesas: r8a77990: Add QSPI[01] pins, groups and functions Lad Prabhakar
2020-11-20 9:19 ` Geert Uytterhoeven
2020-11-20 9:39 ` Lad, Prabhakar [this message]
2020-11-19 13:09 ` [PATCH 2/4] pinctrl: renesas: r8a77951: " Lad Prabhakar
2020-11-20 8:38 ` Geert Uytterhoeven
2020-11-19 13:09 ` [PATCH 3/4] pinctrl: renesas: r8a7796: " Lad Prabhakar
2020-11-20 8:42 ` Geert Uytterhoeven
2020-11-20 8:44 ` Geert Uytterhoeven
2020-11-19 13:09 ` [PATCH 4/4] pinctrl: renesas: r8a77965: " Lad Prabhakar
2020-11-20 8:43 ` Geert Uytterhoeven
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