Re: [PATCH 5/5] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1}

From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Magnus Damm <magnus.damm@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 5/5] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1}
Date: Thu, 21 Jul 2022 13:06:51 +0100	[thread overview]
Message-ID: <CA+V-a8v_Ap404DdXXkA1SU-02s2Y6i+r6psb--MzXOPWOss9nA@mail.gmail.com> (raw)
In-Reply-To: <CAMuHMdXRPpr9othmv9xAOx2a8r=pdP0uZw1xFN9Q0noq1zuw8w@mail.gmail.com>

Hi Geert,

On Thu, Jul 21, 2022 at 12:59 PM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Thu, Jul 21, 2022 at 1:55 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Thu, Jul 21, 2022 at 12:43 PM Geert Uytterhoeven
> > <geert@linux-m68k.org> wrote:
> > > On Thu, Jul 21, 2022 at 1:07 PM Lad, Prabhakar
> > > <prabhakar.csengg@gmail.com> wrote:
> > > > On Thu, Jul 21, 2022 at 11:47 AM Geert Uytterhoeven
> > > > <geert@linux-m68k.org> wrote:
> > > > > On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar
> > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > > > > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0
> > > > > > and ETH1 respectively.
> > > > > >
> > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Thanks for your patch!
> > > > >
> > > > > > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> > > > > > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> > > > > > @@ -94,6 +94,8 @@ phy0: ethernet-phy@7 {
> > > > > >                 compatible = "ethernet-phy-id0022.1640",
> > > > > >                              "ethernet-phy-ieee802.3-c22";
> > > > > >                 reg = <7>;
> > > > > > +               interrupt-parent = <&irqc>;
> > > > > > +               interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> > > > >
> > > > > 2?
> > > > >
> > > > IRQ2 = SPI 3, the driver expects the SPI number and is used as index
> > > > [0] to map the interrupt in the GIC.
> > > >
> > > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/irqchip/irq-renesas-rzg2l.c?h=next-20220720#n291
> > >
> > > Using the SPI number sounds strange to me, as the consumer
> > > (Ethernet PHY) is linked to the IRQC, not to the GIC directly.
> > >
> > Right, are you suggesting that I tweak the driver? The other problem
> > is how do we differentiate NMI and IRQ0? How about we add macros for
> > IRQ0-7 and use them in the DTS?
> >
> > > > > "The first cell should contain external interrupt number (IRQ0-7)"
> > > > >
> > > > Probably I need to reword this to "The first cell should contain the
> > > > SPI number for IRQ0-7/NMI interrupt lines" ?
> > >
> > > Oh, so zero is the NMI?
> > > And 1-8 are IRQ0-7.
> > >
> > Yes that's right.
>
> I don't think it was ever mentioned that the NMI was exposed, too.
>
Sorry for not making this clearer.

> Using macros sounds fine to me.
>
Ok, I will send a v2 (just this patch alone) with the macros added as
a separate patch in rzg2l-pinctrl.h?

Cheers,
Prabhakar

> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds