Re: [PATCH 2/2] drm/i915/cnl: Fix PLL initialization for HDMI.

From: "Ausmus, James" <james.ausmus@intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Intel GFX <intel-gfx@lists.freedesktop.org>,
	Paulo Zanoni <paulo.r.zanoni@intel.com>,
	Kahola@freedesktop.org
Subject: Re: [PATCH 2/2] drm/i915/cnl: Fix PLL initialization for HDMI.
Date: Wed, 4 Oct 2017 12:34:27 -0700	[thread overview]
Message-ID: <CAA1Hj7SEeyX-93qc66fDNfPki==Evt1GKwVoDxmN3i28wqeFmg@mail.gmail.com> (raw)
In-Reply-To: <20171003220859.21352-3-rodrigo.vivi@intel.com>

On Tue, Oct 3, 2017 at 3:08 PM, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> HDMI Mode selection on CNL is on CFGCR0 for that PLL, not
> on in a global CTRL1 as it was on SKL.
>
> The original patch addressed this difference, but leaving behind
> this single entry here. So we were checking the wrong bits during
> the PLL initialization and consequently avoiding the CFGCR1 setup
> during HDMI initialization. Luckly when only HDMI was in use BIOS
> had already setup this for us. But the dual display with hot plug
> were messed up.
>
> Fixes: a927c927de34 ("drm/i915/cnl: Initialize PLLs")
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Kahola, Mika <mika.kahola@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: James Ausmus <james.ausmus@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 55997389a29f..032fd915e929 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2000,7 +2000,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
>
>         /* 3. Configure DPLL_CFGCR0 */
>         /* Avoid touch CFGCR1 if HDMI mode is not enabled */
> -       if (pll->state.hw_state.cfgcr0 & DPLL_CTRL1_HDMI_MODE(pll->id)) {
> +       if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
>                 val = pll->state.hw_state.cfgcr1;
>                 I915_WRITE(CNL_DPLL_CFGCR1(pll->id), val);
>                 /* 4. Reab back to ensure writes completed */
> --
> 2.13.5
>
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> Intel-gfx@lists.freedesktop.org
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-- 


James Ausmus
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