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From: Anup Patel <anup@brainfault.org>
To: Atish Patra <atishp@atishpatra.org>
Cc: "linux-kernel@vger.kernel.org List"
	<linux-kernel@vger.kernel.org>, Atish Patra <atishp@rivosinc.com>,
	 Alexandre Ghiti <alex@ghiti.fr>, Anup Patel <anup.patel@wdc.com>,
	 Greentime Hu <greentime.hu@sifive.com>,
	Guo Ren <guoren@linux.alibaba.com>,
	 Heinrich Schuchardt <xypron.glpk@gmx.de>,
	Ingo Molnar <mingo@kernel.org>,
	 Jisheng Zhang <jszhang@kernel.org>,
	kvm-riscv@lists.infradead.org,  KVM General <kvm@vger.kernel.org>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	 Marc Zyngier <maz@kernel.org>,
	Nanyong Sun <sunnanyong@huawei.com>,
	 Nick Kossifidis <mick@ics.forth.gr>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Paul Walmsley <paul.walmsley@sifive.com>,
	Pekka Enberg <penberg@kernel.org>,
	 Vincent Chen <vincent.chen@sifive.com>,
	Vitaly Wool <vitaly.wool@konsulko.com>
Subject: Re: [RFC 4/6] RISC-V: Move the entire hart selection via lottery to SMP
Date: Mon, 13 Dec 2021 18:27:27 +0530	[thread overview]
Message-ID: <CAAhSdy2NydGsa1Mw-hmJRNeCkQh=z_Q4ob5nTr1ZQDPTRjHDaw@mail.gmail.com> (raw)
In-Reply-To: <20211204002038.113653-5-atishp@atishpatra.org>

On Sat, Dec 4, 2021 at 5:51 AM Atish Patra <atishp@atishpatra.org> wrote:
>
> From: Atish Patra <atishp@rivosinc.com>
>
> The booting hart selection via lottery is only useful for SMP systems.
> Moreover, the lottery selection is only necessary for systems using
> spinwait booting method. It is better to keep the entire lottery
> selection together so that it can be disabled in future.
>
> Move the lottery selection code to under CONFIG_SMP.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>

Looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup

> ---
>  arch/riscv/kernel/head.S | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index 6f8e99eac6a1..9f16bfe9307e 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -264,8 +264,8 @@ pmp_done:
>         blt a0, t0, .Lgood_cores
>         tail .Lsecondary_park
>  .Lgood_cores:
> -#endif
>
> +       /* The lottery system is only required for spinwait booting method */
>  #ifndef CONFIG_XIP_KERNEL
>         /* Pick one hart to run the main boot sequence */
>         la a3, hart_lottery
> @@ -284,6 +284,10 @@ pmp_done:
>         /* first time here if hart_lottery in RAM is not set */
>         beq t0, t1, .Lsecondary_start
>
> +#endif /* CONFIG_XIP */
> +#endif /* CONFIG_SMP */
> +
> +#ifdef CONFIG_XIP_KERNEL
>         la sp, _end + THREAD_SIZE
>         XIP_FIXUP_OFFSET sp
>         mv s0, a0
> @@ -340,8 +344,8 @@ clear_bss_done:
>         call soc_early_init
>         tail start_kernel
>
> -.Lsecondary_start:
>  #ifdef CONFIG_SMP
> +.Lsecondary_start:
>         /* Set trap vector to spin forever to help debug */
>         la a3, .Lsecondary_park
>         csrw CSR_TVEC, a3
> --
> 2.33.1
>
>
> --
> kvm-riscv mailing list
> kvm-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/kvm-riscv

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  reply	other threads:[~2021-12-13 12:58 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-04  0:20 [RFC 0/6] Sparse HART id support Atish Patra
2021-12-04  0:20 ` Atish Patra
2021-12-04  0:20 ` [RFC 1/6] RISC-V: Avoid using per cpu array for ordered booting Atish Patra
2021-12-04  0:20   ` Atish Patra
2021-12-13 12:48   ` Anup Patel
2021-12-13 12:48     ` Anup Patel
2021-12-13 21:05     ` Atish Patra
2021-12-13 21:05       ` Atish Patra
2021-12-04  0:20 ` [RFC 2/6] RISC-V: Do not print the SBI version during HSM extension boot print Atish Patra
2021-12-04  0:20   ` Atish Patra
2021-12-13 12:49   ` Anup Patel
2021-12-13 12:49     ` Anup Patel
2021-12-04  0:20 ` [RFC 3/6] RISC-V: Use __cpu_up_stack/task_pointer only for spinwait method Atish Patra
2021-12-04  0:20   ` Atish Patra
2021-12-13 12:50   ` Anup Patel
2021-12-13 12:50     ` Anup Patel
2021-12-13 12:59   ` Marc Zyngier
2021-12-13 12:59     ` Marc Zyngier
2021-12-13 21:12     ` Atish Patra
2021-12-13 21:12       ` Atish Patra
2021-12-04  0:20 ` [RFC 4/6] RISC-V: Move the entire hart selection via lottery to SMP Atish Patra
2021-12-13 12:57   ` Anup Patel [this message]
2021-12-04  0:20 ` [RFC 5/6] RISC-V: Move spinwait booting method to its own config Atish Patra
2021-12-04  0:20   ` Atish Patra
2021-12-04  0:40   ` Randy Dunlap
2021-12-04  0:40     ` Randy Dunlap
2021-12-13 13:01   ` Anup Patel
2021-12-13 13:01     ` Anup Patel
2021-12-13 21:08     ` Atish Patra
2021-12-13 21:08       ` Atish Patra
2021-12-04  0:20 ` [RFC 6/6] RISC-V: Do not use cpumask data structure for hartid bitmap Atish Patra
2021-12-04  0:20   ` Atish Patra
2021-12-06 15:28 ` [RFC 0/6] Sparse HART id support Rob Herring
2021-12-06 15:28   ` Rob Herring
2021-12-13 21:27   ` Atish Patra
2021-12-13 21:27     ` Atish Patra
2021-12-13 23:11     ` Rob Herring
2021-12-13 23:11       ` Rob Herring
2021-12-14  0:58       ` Atish Patra
2021-12-14  0:58         ` Atish Patra

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