Re: [PATCH 1/3] drm/i915: Enable FBC at Haswell.

From: Rodrigo Vivi <rodrigo.vivi@gmail.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 1/3] drm/i915: Enable FBC at Haswell.
Date: Tue, 16 Apr 2013 10:23:17 -0300	[thread overview]
Message-ID: <CABVU7+uvCznKzw+tqOT078zO5r63wureSwJYmjh5wEAHFnzCyw@mail.gmail.com> (raw)
In-Reply-To: <20130416102847.GG4469@intel.com>

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Yeah, this makes sense. Yes, I tested many times here, with 0 at bit 28 I
always got that bug with missing updates, In the way it is it always worked
fine.

On Tue, Apr 16, 2013 at 7:28 AM, Ville Syrjälä <
ville.syrjala@linux.intel.com> wrote:

> On Mon, Apr 15, 2013 at 06:14:46PM -0300, Rodrigo Vivi wrote:
> > On Wed, Apr 10, 2013 at 5:18 AM, Ville Syrjälä <
> > ville.syrjala@linux.intel.com> wrote:
> >
> > > On Tue, Apr 09, 2013 at 03:13:10PM -0300, Rodrigo Vivi wrote:
> > > > On Tue, Apr 9, 2013 at 5:35 AM, Ville Syrjälä <
> > > ville.syrjala@linux.intel.com
> > > > > wrote:
> > > >
> > > > > On Mon, Apr 08, 2013 at 06:49:42PM -0300, Rodrigo Vivi wrote:
> > > > > > This patch introduce Frame Buffer Compression (FBC) support for
> HSW.
> > > > > > It adds a new function haswell_enable_fbc to avoid getting
> > > > > > ironlake_enable_fbc messed with many IS_HASWELL checks.
> > > > > >
> > > > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> > > > > > ---
> > > > > >  drivers/gpu/drm/i915/i915_drv.c |  1 +
> > > > > >  drivers/gpu/drm/i915/i915_reg.h |  6 ++++++
> > > > > >  drivers/gpu/drm/i915/intel_pm.c | 44
> > > > > ++++++++++++++++++++++++++++++++++++++++-
> > > > > >  3 files changed, 50 insertions(+), 1 deletion(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > > > > b/drivers/gpu/drm/i915/i915_drv.c
> > > > > > index 0cfc778..88fd6fb 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > > > @@ -291,6 +291,7 @@ static const struct intel_device_info
> > > > > intel_haswell_m_info = {
> > > > > >       GEN7_FEATURES,
> > > > > >       .is_haswell = 1,
> > > > > >       .is_mobile = 1,
> > > > > > +     .has_fbc = 1,
> > > > > >  };
> > > > > >
> > > > > >  static const struct pci_device_id pciidlist[] = {            /*
> aka
> > > */
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > index 5e91fbb..cb8e213 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > @@ -849,6 +849,12 @@
> > > > > >  #define   SNB_CPU_FENCE_ENABLE       (1<<29)
> > > > > >  #define DPFC_CPU_FENCE_OFFSET        0x100104
> > > > > >
> > > > > > +/* Framebuffer compression for Haswell */
> > > > > > +#define HSW_FBC_RT_BASE                      0x7020
> > > > > > +#define   HSW_FBC_RT_BASE_ADDR_SHIFT 12
> > > > > > +
> > > > > > +#define   HSW_DPFC_CTL_FENCE_EN              (1<<28)
> > > > > > +#define   HSW_DPFC_CTL_DISABLE_SLB_INIT      (1<<15)
> > > > > >
> > > > > >  /*
> > > > > >   * GPIO regs
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > > > b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > index 27f94cd..94e1c3a 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > @@ -253,6 +253,43 @@ static bool ironlake_fbc_enabled(struct
> > > drm_device
> > > > > *dev)
> > > > > >       return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
> > > > > >  }
> > > > > >
> > > > > > +static void haswell_enable_fbc(struct drm_crtc *crtc, unsigned
> long
> > > > > interval)
> > > > > > +{
> > > > > > +     struct drm_device *dev = crtc->dev;
> > > > > > +     struct drm_i915_private *dev_priv = dev->dev_private;
> > > > > > +     struct drm_framebuffer *fb = crtc->fb;
> > > > > > +     struct intel_framebuffer *intel_fb =
> to_intel_framebuffer(fb);
> > > > > > +     struct drm_i915_gem_object *obj = intel_fb->obj;
> > > > > > +     struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > > > > > +     int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
> > > > > DPFC_CTL_PLANEB;
> > > > > > +     unsigned long stall_watermark = 200;
> > > > > > +     u32 dpfc_ctl;
> > > > > > +
> > > > > > +     dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
> > > > > > +     dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
> > > > >
> > > > > Accroding to BSpec FBC is always tied to plane A. Bit 30 is MBZ.
> > > > >
> > > >
> > > > Yeah, you are right. I'm going to add a verification at  begining
> like:
> > > >      if (intel_crtc->plane != PLANE_A) {
> > > >     dev_priv->no_fbc_reason = FBC_BAD_PLANE;
> > > >     return;
> > > > }
> > > >
> > > >
> > > > > Maybe fix up plane C FBC support for IVB while you're poking at the
> > > > > general direction?
> > > > >
> > > >
> > > > Actually I wasn't trying general directions since I splited it out.
> It
> > > was
> > > > just bad copy and paste actually.
> > >
> > > I'm not a fan of copy pasting code and letting the old code paths rot.
> > >
> > > > >
> > > > > > +     dpfc_ctl |= (HSW_DPFC_CTL_FENCE_EN | obj->fence_reg);
> > > > >
> > > > > The CPU fence field must be written with 0. SNB/IVB could do with
> the
> > > > > same fix.
> > > > >
> > > >
> > > > Where did you get this restriction for HSW?
> > >
> > > BSpec.
> > >
> >
> > Are you talking about bit 28 of 43208h DevHSW?
>
> Bits 0:3 of the same register.
>
> > I couldn't find this restriction anywhere.
> > Besides that, setting it to 0 made me experience bugs like missing some
> > small screen updates. I mean, when it is 0 I missed many "****" when
> typing
> > my login password.
> > When it is set FBC works fine.
>
> This is what BSpec is telling us to program:
>
> FBC_CTL
>  28 = ?
>  0:3 = 0
>
> DPFC_CONTROL_SA
>  29 = 1
>  0:4 = fence number
>
> So the FBC_CTL bit 28 is not clear. BSpec doesn't say whether it should
> be 0 or 1. Did you try both values for that bit?
>
> --
> Ville Syrjälä
> Intel OTC
>

-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

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