From: Andy Chiu <andy.chiu@sifive.com>
To: Guo Ren <guoren@kernel.org>
Cc: palmer@dabbelt.com, paul.walmsley@sifive.com,
aou@eecs.berkeley.edu, rostedt@goodmis.org, mingo@redhat.com,
peterz@infradead.org, jpoimboe@kernel.org, jbaron@akamai.com,
ardb@kernel.org, greentime.hu@sifive.com, zong.li@sifive.com,
kernel@esmil.dk, linux-riscv@lists.infradead.org,
Jim Shu <jim.shu@sifive.com>,
Ruinland Tsai <ruinland.tsai@sifive.com>
Subject: Re: [PATCH RFC v2 riscv/for-next 3/5] riscv: ftrace: use indirect jump to work with kernel preemption
Date: Sat, 17 Sep 2022 02:04:11 +0100 [thread overview]
Message-ID: <CABgGipWBOZx+c0i5B9xArTRxa6-4yAbeByWXr7v8MSf7AATfxg@mail.gmail.com> (raw)
In-Reply-To: <CAJF2gTSn3_cDYsF9D8dt-br2Wf_M8y02A09xgRq8kXi91sN3Aw@mail.gmail.com>
Hi Guo,
On Wed, Sep 14, 2022 at 2:45 PM Guo Ren <guoren@kernel.org> wrote:
>
> I really appreciate you finding the bug, great job.
Thanks, :)
>
> On Tue, Sep 13, 2022 at 5:44 PM Andy Chiu <andy.chiu@sifive.com> wrote:
Consider this case happens on a preemptive kernel, with stop_machine.
And all of stop_machine's sub-functions were marked as no trace.
> > p: patched area performed by dynamic ftrace
> > ftrace_prologue:
> > p| REG_S ra, -SZREG(sp)
> > p| auipc ra, 0x? ------------> preempted
> > ...
> > change ftrace function
> > ...
> > p| jalr -?(ra) <------------- switched back
>
> When auipc + jalr -> nop, is safe, right? Because when switched back,
> jalr -> nop.
> When nop -> auipc + jalr, is buggy, right? Because when switched back,
> nop -> jalr, the ra's value is not expected.
>
> Some machines with instruction fusion won't be affected, because they
> would merge auipc + jalr into one macro-op.
This might not be safe as well, if auipc and jalr happened to sit on a
different cache line. And if there were a cache hit for the line
having the auipc and miss for the jalr after switching back. I do not
really sure if this is possible in practice.
> Qemu shouldn't be broken, because auipc + jalr is always in the same
> tcg block, so no chance for interruption between them.
In fact, qemu is broken. I had not thought of that before I got your
reply. But I believe that there is a size limit for each tcg block,
and the auipc and jalr just locate in a separate tcg block.
Regards,
Andy
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next prev parent reply other threads:[~2022-09-17 1:04 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-13 9:42 [PATCH RFC v2 riscv/for-next 0/5] Enable ftrace with kernel preemption for RISC-V Andy Chiu
2022-09-13 9:42 ` [PATCH RFC v2 riscv/for-next 1/5] riscv: align ftrace to 4 Byte boundary and increase ftrace prologue size Andy Chiu
2022-09-15 13:53 ` Guo Ren
2022-09-17 1:15 ` Andy Chiu
2022-09-13 9:42 ` [PATCH RFC v2 riscv/for-next 2/5] riscv: export patch_insn_write Andy Chiu
2022-09-13 9:42 ` [PATCH RFC v2 riscv/for-next 3/5] riscv: ftrace: use indirect jump to work with kernel preemption Andy Chiu
2022-09-14 13:45 ` Guo Ren
2022-09-15 13:30 ` Guo Ren
2022-09-17 1:04 ` Andy Chiu [this message]
2022-09-17 10:56 ` Guo Ren
2024-02-20 14:17 ` Evgenii Shatokhin
2022-09-13 9:42 ` [PATCH RFC v2 riscv/for-next 4/5] riscv: ftrace: do not use stop_machine to update code Andy Chiu
2022-09-13 9:42 ` [PATCH RFC v2 riscv/for-next 5/5] riscv: align arch_static_branch function Andy Chiu
2022-09-14 14:06 ` Guo Ren
2022-09-16 23:54 ` Andy Chiu
2022-09-17 0:22 ` Guo Ren
2022-09-17 18:17 ` [PATCH] riscv: jump_label: Optimize size with RISCV_ISA_C guoren
2022-09-17 18:38 ` [PATCH RFC v2 riscv/for-next 5/5] riscv: align arch_static_branch function guoren
2022-09-17 23:49 ` Guo Ren
2022-09-17 23:59 ` Guo Ren
2022-09-18 0:12 ` Jessica Clarke
2022-09-18 0:46 ` Guo Ren
2022-09-14 14:24 ` Jessica Clarke
2022-09-15 1:47 ` Guo Ren
2022-09-15 2:34 ` Jessica Clarke
2024-02-13 19:42 ` [PATCH RFC v2 riscv/for-next 0/5] Enable ftrace with kernel preemption for RISC-V Evgenii Shatokhin
2024-02-21 5:27 ` Andy Chiu
2024-02-21 16:55 ` Evgenii Shatokhin
2024-03-06 20:57 ` Alexandre Ghiti
2024-03-07 8:35 ` Evgenii Shatokhin
2024-03-07 12:27 ` Andy Chiu
2024-03-07 13:21 ` Alexandre Ghiti
2024-03-07 15:57 ` Samuel Holland
2024-03-11 14:24 ` Andy Chiu
2024-03-19 14:50 ` Alexandre Ghiti
2024-03-19 14:58 ` Conor Dooley
2024-03-20 16:37 ` Andy Chiu
2024-03-18 15:31 ` Andy Chiu
2024-03-19 15:32 ` Evgenii Shatokhin
2024-03-20 16:38 ` Andy Chiu
2024-03-19 17:37 ` Alexandre Ghiti
2024-03-20 16:36 ` Andy Chiu
2024-03-21 11:02 ` Alexandre Ghiti
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