Re: [PATCH for-5.2 16/19] aspeed/sdmc: Perform memory training

From: Joel Stanley <joel@jms.id.au>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: "Andrew Jeffery" <andrew@aj.id.au>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	qemu-arm <qemu-arm@nongnu.org>, "Cédric Le Goater" <clg@kaod.org>,
	"QEMU Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH for-5.2 16/19] aspeed/sdmc: Perform memory training
Date: Fri, 7 Aug 2020 00:10:34 +0000	[thread overview]
Message-ID: <CACPK8XcN0Oq-4uKjxUg=DR6KZSkYqs+AFnM=SFoxwWiB9rXktw@mail.gmail.com> (raw)
In-Reply-To: <56f83c0b-b5eb-241e-c848-56f038633398@amsat.org>

On Thu, 6 Aug 2020 at 13:38, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:

> > @@ -206,6 +206,19 @@ static void aspeed_sdmc_reset(DeviceState *dev)
> >
> >      /* Set ram size bit and defaults values */
> >      s->regs[R_CONF] = asc->compute_conf(s, 0);
> > +
> > +    /*
> > +     * PHY status:
> > +     *  - set phy status ok (set bit 1)
> > +     *  - initial PVT calibration ok (clear bit 3)
> > +     *  - runtime calibration ok (clear bit 5)
> > +     */
> > +    s->regs[0x100] = BIT(1);
>
> This is usually implemented with a one-shot timer, see
> sd_ocr_powerup() in hw/sd/sd.c (migration is handled).

You mean we could have the calibration done bits become set at a later time?

It would be hard to work out what to do. We have no documentation for
the register, I modelled it based on the code in u-boot doing this:

         /* make sure DDR-PHY is ready before access */
        do {
                reg = readl(priv->phy_status) & BIT(1);
        } while(reg == 0);

So I think there would be limited value in modelling it.

Thanks for the suggestion though, I'll keep the one shot timer idea in
mind for future models.

Cheers,

Joel