Re: [PATCH] hw/misc: zynq_slcr: set SLC_RST bit in REBOOT_STATUS register

From: Peter Maydell <peter.maydell@linaro.org>
To: Gregory Anders <greg@gpanders.com>
Cc: qemu-devel@nongnu.org,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	 Alistair Francis <alistair@alistair23.me>
Subject: Re: [PATCH] hw/misc: zynq_slcr: set SLC_RST bit in REBOOT_STATUS register
Date: Fri, 1 Mar 2024 16:40:32 +0000	[thread overview]
Message-ID: <CAFEAcA-wrdUaH55ZmoCQAQ=zV=seaCo2hciXys_p4tKE08Tf3w@mail.gmail.com> (raw)
In-Reply-To: <20240227222227.74935-1-greg@gpanders.com>

On Wed, 28 Feb 2024 at 01:40, Gregory Anders <greg@gpanders.com> wrote:
>
> When the CPU is reset using PSS_RST_CTRL in the SLCR, bit 19 in
> REBOOT_STATUS should be set.
>
> Refer to page 1602 of the Xilinx Zynq 7000 Technical Reference Manual.
>
> Signed-off-by: Gregory Anders <greg@gpanders.com>
> ---
>  hw/misc/zynq_slcr.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
> index d2ac2e77f2..a8f1792bf6 100644
> --- a/hw/misc/zynq_slcr.c
> +++ b/hw/misc/zynq_slcr.c
> @@ -120,6 +120,7 @@ REG32(RS_AWDT_CTRL, 0x24c)
>  REG32(RST_REASON, 0x250)
>
>  REG32(REBOOT_STATUS, 0x258)
> +    FIELD(REBOOT_STATUS, SLC_RST, 19, 1)
>  REG32(BOOT_MODE, 0x25c)
>
>  REG32(APU_CTRL, 0x300)
> @@ -562,6 +563,7 @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
>      switch (offset) {
>      case R_PSS_RST_CTRL:
>          if (FIELD_EX32(val, PSS_RST_CTRL, SOFT_RST)) {
> +            s->regs[R_REBOOT_STATUS] |= R_REBOOT_STATUS_SLC_RST_MASK;
>              qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
>          }
>          break;
> --

The manual also says that "This field is written by ROM code",
so as a model of the hardware should QEMU be writing it?

I've cc'd the Zynq maintainers for their opinion.

thanks
-- PMM