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From: Daniel Vetter <daniel@ffwll.ch>
To: Lucas De Marchi <lucas.demarchi@intel.com>,
	Dave Airlie <airlied@redhat.com>
Cc: intel-gfx <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs
Date: Wed, 8 Jul 2020 19:08:11 +0200	[thread overview]
Message-ID: <CAKMK7uFHfGXz4WxeVtJnhmp6ueJ3VF1y581Ne-KzADEoxxMRpA@mail.gmail.com> (raw)
In-Reply-To: <20200701235339.32608-4-lucas.demarchi@intel.com>

On Thu, Jul 2, 2020 at 1:55 AM Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>
> From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
>
> Add the PCI ID for DG1, but keep it out of the table we use to register
> the driver. At this point we can't consider the driver ready to bind to
> the device since we basically miss support for everything. When more
> support is merged we can enable it to work partially for example as a
> display-only driver.
>
> v2: remove DG1 from the pci table and reword commit message (Lucas)
>
> Bspec: 44463
>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> # v1
> ---
>  drivers/gpu/drm/i915/i915_pci.c | 2 +-
>  include/drm/i915_pciids.h       | 4 ++++
>  2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 58cceeaa0ffa..8cae64adbb23 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -900,7 +900,7 @@ static const struct intel_device_info rkl_info = {
>         .has_master_unit_irq = 1, \
>         .is_dgfx = 1
>
> -static const struct intel_device_info intel_dg1_info = {
> +static const struct intel_device_info dg1_info = {

Looks like a misplaced hunk here, but aside from that, on the "let's
just not add the pci id":

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Also adding Dave just as fyi.
-Daniel

>         GEN12_DGFX_FEATURES,
>         PLATFORM(INTEL_DG1),
>         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index bc989de2aac2..f44fe822880d 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -614,4 +614,8 @@
>         INTEL_VGA_DEVICE(0x4C90, info), \
>         INTEL_VGA_DEVICE(0x4C9A, info)
>
> +/* DG1 */
> +#define INTEL_DG1_IDS(info) \
> +       INTEL_VGA_DEVICE(0x4905, info)
> +
>  #endif /* _I915_PCIIDS_H */
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2020-07-08 17:08 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 01/28] drm/i915: Add has_master_unit_irq flag Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 02/28] drm/i915/dg1: add initial DG-1 definitions Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs Lucas De Marchi
2020-07-02  6:00   ` kernel test robot
2020-07-02  6:00     ` kernel test robot
2020-07-09 20:01     ` Lucas De Marchi
2020-07-09 20:56       ` Lucas De Marchi
2020-07-02 12:37   ` kernel test robot
2020-07-02 12:37     ` kernel test robot
2020-07-08 17:08   ` Daniel Vetter [this message]
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 04/28] drm/i915/dg1: add support for the master unit interrupt Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 05/28] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 06/28] drm/i915/dg1: Add fake PCH Lucas De Marchi
2020-07-08  7:28   ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 07/28] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 08/28] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 09/28] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 10/28] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 11/28] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 12/28] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 13/28] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 14/28] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 15/28] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 16/28] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 17/28] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 18/28] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 19/28] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
2020-07-08  7:17   ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 20/28] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
2020-07-08  7:51   ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 21/28] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
2020-07-08 10:23   ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 22/28] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 23/28] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 24/28] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 25/28] drm/i915/dg1: Load DMC Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 26/28] drm/i915/rkl: Add initial workarounds Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 27/28] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 28/28] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
2020-07-02  0:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev3) Patchwork
2020-07-02  0:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-02  0:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-02  4:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-07-02  7:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev4) Patchwork
2020-07-02  7:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-02  8:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-02 11:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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