Re: [PATCH 2/5] drm/i915: PSR: Remove Low Power HW tracking mask.

From: Daniel Vetter <daniel.vetter@ffwll.ch>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: intel-gfx <intel-gfx@lists.freedesktop.org>,
	Arthur Ranyan <arthur.j.runyan@intel.com>,
	Matthew Garrett <mjg59@srcf.ucam.orgviacodon.org.uk>
Subject: Re: [PATCH 2/5] drm/i915: PSR: Remove Low Power HW tracking mask.
Date: Fri, 19 Jun 2015 22:32:48 +0200	[thread overview]
Message-ID: <CAKMK7uGzWC7Pagq-NA6V=28pd0YjrwX8Raa48TNEFBA6gEhzKg@mail.gmail.com> (raw)
In-Reply-To: <1434653006-5693-2-git-send-email-rodrigo.vivi@intel.com>

On Thu, Jun 18, 2015 at 8:43 PM, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> By Spec we should just mask memup and hotplug detection
> for hardware tracking cases. However we always masked
> LPSP that is for low power tracking support because
> without it PSR was constantly exiting and never really
> getting activated.
>
> Now with runtime PM being enabled by default Matthew
> reported that he was facing missed screen updates. So
> let's remove this undesirable mask and let HW tracking
> take care of cases like this were power saving features
> are also running.
>
> WARNING: With this patch PSR depends on Audio and GPU
> runtime PM to be properly enabled, working on "auto".
> If either audio runtime PM or gpu runtime pm are not
> properly set PSR will constant Exit and Performance
> Counter will be 0.
>
> But the best thing of this patch is that with one more
> HW tracking working the risks of missed blank screen
> are minimized at most.
>
> This affects just core platforms where PSR exit are also
> helped by HW tracking: Haswell, Broadwell and Skylake
> for now.
>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Matthew Garrett <mjg59@srcf.ucam.org via codon.org.uk>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

I guess I don't really understand your description, but it does sound
strange ... runtime pm enabling from my patch is only about D3, power
well changes are still done. And as long as we have anything enabled
(even with PSR) we'll prevent D3.

So the only thing I can think of is that somehow D3 wreaks something
in the PSR setup and that's causing issues. Unfortunately I have no
idea about our hw details around PSR and D3, so no idea. Maybe Art has
some?

> ---
>  drivers/gpu/drm/i915/intel_psr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 5ee0fa5..6549d58 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -400,7 +400,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>
>                 /* Avoid continuous PSR exit by masking memup and hpd */

Need to adjust the comment.

>                 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
> -                          EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
> +                          EDP_PSR_DEBUG_MASK_HPD);
>
>                 /* Enable PSR on the panel */
>                 hsw_psr_enable_sink(intel_dp);
> --
> 2.1.0
>

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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