From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, palmer@dabbelt.com,
zhiwei_liu@linux.alibaba.com, fei2.wu@intel.com,
Weiwei Li <liweiwei@iscas.ac.cn>
Subject: Re: [PATCH v6 05/25] target/riscv: Add a tb flags field for vstart
Date: Tue, 11 Apr 2023 12:07:12 +1000 [thread overview]
Message-ID: <CAKmqyKMWnf_HHXuGSPp1Cov8Oa6rp0wuq2YrN2msPtsBvD7whQ@mail.gmail.com> (raw)
In-Reply-To: <20230325105429.1142530-6-richard.henderson@linaro.org>
On Sat, Mar 25, 2023 at 9:52 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>
> Once we mistook the vstart directly from the env->vstart. As env->vstart is not
> a constant, we should record it in the tb flags if we want to use
> it in translation.
>
> Reported-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Message-Id: <20230324143031.1093-5-zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_helper.c | 1 +
> target/riscv/translate.c | 4 ++--
> target/riscv/insn_trans/trans_rvv.c.inc | 14 +++++++-------
> 4 files changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index d9e0eaaf9b..86a82e25dc 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -657,6 +657,7 @@ FIELD(TB_FLAGS, VMA, 21, 1)
> FIELD(TB_FLAGS, ITRIGGER, 22, 1)
> /* Virtual mode enabled */
> FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
> +FIELD(TB_FLAGS, VSTART_EQ_ZERO, 24, 1)
>
> #ifdef TARGET_RISCV32
> #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 4fdd6fe021..4f0999d50b 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -74,6 +74,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> FIELD_EX64(env->vtype, VTYPE, VTA));
> flags = FIELD_DP32(flags, TB_FLAGS, VMA,
> FIELD_EX64(env->vtype, VTYPE, VMA));
> + flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
> } else {
> flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
> }
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 74d0b9889d..f8c077525c 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -97,7 +97,7 @@ typedef struct DisasContext {
> uint8_t vta;
> uint8_t vma;
> bool cfg_vta_all_1s;
> - target_ulong vstart;
> + bool vstart_eq_zero;
> bool vl_eq_vlmax;
> CPUState *cs;
> TCGv zero;
> @@ -1155,7 +1155,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s;
> ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s;
> ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;
> - ctx->vstart = env->vstart;
> + ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO);
> ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
> ctx->misa_mxl_max = env->misa_mxl_max;
> ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 6297c3b50d..32b3b9a8e5 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -547,7 +547,7 @@ static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int vm)
> */
> static bool vext_check_reduction(DisasContext *s, int vs2)
> {
> - return require_align(vs2, s->lmul) && (s->vstart == 0);
> + return require_align(vs2, s->lmul) && s->vstart_eq_zero;
> }
>
> /*
> @@ -3083,7 +3083,7 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a)
> {
> if (require_rvv(s) &&
> vext_check_isa_ill(s) &&
> - s->vstart == 0) {
> + s->vstart_eq_zero) {
> TCGv_ptr src2, mask;
> TCGv dst;
> TCGv_i32 desc;
> @@ -3112,7 +3112,7 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
> {
> if (require_rvv(s) &&
> vext_check_isa_ill(s) &&
> - s->vstart == 0) {
> + s->vstart_eq_zero) {
> TCGv_ptr src2, mask;
> TCGv dst;
> TCGv_i32 desc;
> @@ -3146,7 +3146,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> vext_check_isa_ill(s) && \
> require_vm(a->vm, a->rd) && \
> (a->rd != a->rs2) && \
> - (s->vstart == 0)) { \
> + s->vstart_eq_zero) { \
> uint32_t data = 0; \
> gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
> TCGLabel *over = gen_new_label(); \
> @@ -3187,7 +3187,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
> !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) &&
> require_vm(a->vm, a->rd) &&
> require_align(a->rd, s->lmul) &&
> - (s->vstart == 0)) {
> + s->vstart_eq_zero) {
> uint32_t data = 0;
> TCGLabel *over = gen_new_label();
> tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
> @@ -3636,7 +3636,7 @@ static bool vcompress_vm_check(DisasContext *s, arg_r *a)
> require_align(a->rs2, s->lmul) &&
> (a->rd != a->rs2) &&
> !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs1, 1) &&
> - (s->vstart == 0);
> + s->vstart_eq_zero;
> }
>
> static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
> @@ -3675,7 +3675,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
> QEMU_IS_ALIGNED(a->rd, LEN) && \
> QEMU_IS_ALIGNED(a->rs2, LEN)) { \
> uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN; \
> - if (s->vstart == 0) { \
> + if (s->vstart_eq_zero) { \
> /* EEW = 8 */ \
> tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \
> vreg_ofs(s, a->rs2), maxsz, maxsz); \
> --
> 2.34.1
>
>
next prev parent reply other threads:[~2023-04-11 2:07 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-25 10:54 [PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups Richard Henderson
2023-03-25 10:54 ` [PATCH v6 01/25] target/riscv: Extract virt enabled state from tb flags Richard Henderson
2023-04-06 2:35 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 02/25] target/riscv: Add a general status enum for extensions Richard Henderson
2023-03-26 12:54 ` liweiwei
2023-04-11 2:05 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 03/25] target/riscv: Encode the FS and VS on a normal way for tb flags Richard Henderson
2023-04-11 1:59 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags Richard Henderson
2023-03-27 1:34 ` liweiwei
2023-03-27 16:22 ` Richard Henderson
2023-03-28 2:34 ` [PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs,vs} " LIU Zhiwei
2023-04-11 2:02 ` [PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs, vs} " Alistair Francis
2023-03-25 10:54 ` [PATCH v6 05/25] target/riscv: Add a tb flags field for vstart Richard Henderson
2023-04-11 2:07 ` Alistair Francis [this message]
2023-03-25 10:54 ` [PATCH v6 06/25] target/riscv: Separate priv from mmu_idx Richard Henderson
2023-03-28 2:39 ` LIU Zhiwei
2023-04-11 2:08 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 07/25] target/riscv: Reduce overhead of MSTATUS_SUM change Richard Henderson
2023-03-28 2:41 ` LIU Zhiwei
2023-04-11 2:11 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 08/25] accel/tcg: Add cpu_ld*_code_mmu Richard Henderson
2023-04-11 3:10 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 09/25] target/riscv: Use cpu_ld*_code_mmu for HLVX Richard Henderson
2023-04-11 3:12 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 10/25] target/riscv: Handle HLV, HSV via helpers Richard Henderson
2023-04-11 3:34 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT Richard Henderson
2023-04-11 3:36 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 12/25] target/riscv: Introduce mmuidx_sum Richard Henderson
2023-04-11 3:39 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 13/25] target/riscv: Introduce mmuidx_priv Richard Henderson
2023-03-27 2:07 ` LIU Zhiwei
2023-03-27 16:29 ` Richard Henderson
2023-03-28 1:33 ` LIU Zhiwei
2023-03-28 1:54 ` LIU Zhiwei
2023-03-28 14:27 ` Richard Henderson
2023-04-11 3:53 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 14/25] target/riscv: Introduce mmuidx_2stage Richard Henderson
2023-04-11 3:55 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 15/25] target/riscv: Move hstatus.spvp check to check_access_hlsv Richard Henderson
2023-04-11 3:56 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 16/25] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index Richard Henderson
2023-04-11 4:02 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 17/25] target/riscv: Check SUM in the correct register Richard Henderson
2023-04-11 4:25 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 18/25] target/riscv: Hoist second stage mode change to callers Richard Henderson
2023-04-11 4:25 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 19/25] target/riscv: Hoist pbmte and hade out of the level loop Richard Henderson
2023-04-11 4:26 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 20/25] target/riscv: Move leaf pte processing out of " Richard Henderson
2023-04-11 4:30 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 21/25] target/riscv: Suppress pte update with is_debug Richard Henderson
2023-04-11 4:30 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 22/25] target/riscv: Don't modify SUM " Richard Henderson
2023-04-11 4:31 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 23/25] target/riscv: Merge checks for reserved pte flags Richard Henderson
2023-04-11 4:32 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 24/25] target/riscv: Reorg access check in get_physical_address Richard Henderson
2023-04-11 4:55 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 25/25] target/riscv: Reorg sum " Richard Henderson
2023-04-11 5:36 ` Alistair Francis
2023-03-26 5:17 ` [PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups Richard Henderson
2023-03-26 14:18 ` liweiwei
2023-03-27 16:43 ` Daniel Henrique Barboza
2023-03-28 1:22 ` Wu, Fei
2023-04-04 6:42 ` Wu, Fei
2023-04-04 7:11 ` LIU Zhiwei
2023-04-04 7:23 ` Wu, Fei
2023-04-11 5:38 ` Alistair Francis
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