From: Alistair Francis <alistair23@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PULL 00/15] riscv-to-apply queue
Date: Mon, 13 Jul 2020 17:37:04 -0700 [thread overview]
Message-ID: <CAKmqyKP+bRqky7YB6Gv-1uybvZfGnH2sRh0g_9mLoh=1+03GcA@mail.gmail.com> (raw)
In-Reply-To: <20200714003254.4044149-1-alistair.francis@wdc.com>
On Mon, Jul 13, 2020 at 5:43 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> The following changes since commit 20c1df5476e1e9b5d3f5b94f9f3ce01d21f14c46:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200713-pull-request' into staging (2020-07-13 16:58:44 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200713
>
> for you to fetch changes up to cfad709bceb629a4ebeb5d8a3acd1871b9a6436b:
>
> target/riscv: Fix pmp NA4 implementation (2020-07-13 17:25:37 -0700)
Sorry these are a little late, I was hoping to send them out last week
but I was chasing down some bugs and waiting on a few patches.
Alistair
>
> ----------------------------------------------------------------
> This is a colection of bug fixes and small imrprovements for RISC-V.
>
> This includes some vector extensions fixes, a PMP bug fix, OpenTitan
> UART bug fix and support for OpenSBI dynamic firmware.
>
> ----------------------------------------------------------------
> Alexandre Mergnat (1):
> target/riscv: Fix pmp NA4 implementation
>
> Alistair Francis (2):
> hw/char: Convert the Ibex UART to use the qdev Clock model
> hw/char: Convert the Ibex UART to use the registerfields API
>
> Atish Patra (4):
> riscv: Unify Qemu's reset vector code path
> RISC-V: Copy the fdt in dram instead of ROM
> riscv: Add opensbi firmware dynamic support
> RISC-V: Support 64 bit start address
>
> Bin Meng (3):
> MAINTAINERS: Add an entry for OpenSBI firmware
> hw/riscv: virt: Sort the SoC memmap table entries
> hw/riscv: Modify MROM size to end at 0x10000
>
> Frank Chang (4):
> target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
> target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
> target/riscv: fix return value of do_opivx_widen()
> target/riscv: fix vill bit index in vtype register
>
> Liao Pingfang (1):
> tcg/riscv: Remove superfluous breaks
>
> include/hw/char/ibex_uart.h | 79 ++++++++--------
> include/hw/riscv/boot.h | 7 ++
> include/hw/riscv/boot_opensbi.h | 58 ++++++++++++
> target/riscv/cpu.h | 2 +-
> hw/char/ibex_uart.c | 158 ++++++++++++++++++--------------
> hw/riscv/boot.c | 107 +++++++++++++++++++++
> hw/riscv/sifive_u.c | 53 ++++++-----
> hw/riscv/spike.c | 59 ++++--------
> hw/riscv/virt.c | 63 ++++---------
> target/riscv/insn_trans/trans_rvv.inc.c | 9 +-
> target/riscv/pmp.c | 2 +-
> tcg/riscv/tcg-target.inc.c | 2 -
> MAINTAINERS | 7 ++
> 13 files changed, 387 insertions(+), 219 deletions(-)
> create mode 100644 include/hw/riscv/boot_opensbi.h
>
next prev parent reply other threads:[~2020-07-14 0:48 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
2020-07-14 0:32 ` [PULL 01/15] MAINTAINERS: Add an entry for OpenSBI firmware Alistair Francis
2020-07-14 0:32 ` [PULL 02/15] hw/riscv: virt: Sort the SoC memmap table entries Alistair Francis
2020-07-14 0:32 ` [PULL 03/15] riscv: Unify Qemu's reset vector code path Alistair Francis
2020-07-14 0:32 ` [PULL 04/15] RISC-V: Copy the fdt in dram instead of ROM Alistair Francis
2021-07-13 10:43 ` Peter Maydell
2021-07-14 6:35 ` Alistair Francis
2020-07-14 0:32 ` [PULL 05/15] riscv: Add opensbi firmware dynamic support Alistair Francis
2020-07-14 0:32 ` [PULL 06/15] RISC-V: Support 64 bit start address Alistair Francis
2020-07-14 0:32 ` [PULL 07/15] hw/riscv: Modify MROM size to end at 0x10000 Alistair Francis
2020-07-14 0:32 ` [PULL 08/15] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion Alistair Francis
2020-07-14 0:32 ` [PULL 09/15] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() Alistair Francis
2020-07-14 0:32 ` [PULL 10/15] target/riscv: fix return value of do_opivx_widen() Alistair Francis
2020-07-14 0:32 ` [PULL 11/15] target/riscv: fix vill bit index in vtype register Alistair Francis
2020-07-14 0:32 ` [PULL 12/15] hw/char: Convert the Ibex UART to use the qdev Clock model Alistair Francis
2020-07-14 0:32 ` [PULL 13/15] hw/char: Convert the Ibex UART to use the registerfields API Alistair Francis
2020-07-14 0:32 ` [PULL 14/15] tcg/riscv: Remove superfluous breaks Alistair Francis
2020-07-14 0:32 ` [PULL 15/15] target/riscv: Fix pmp NA4 implementation Alistair Francis
2020-07-14 0:37 ` Alistair Francis [this message]
2020-07-14 18:39 ` [PULL 00/15] riscv-to-apply queue Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2024-03-22 8:53 Alistair Francis
2024-03-22 12:58 ` Peter Maydell
2024-03-22 17:16 ` Michael Tokarev
2024-03-22 19:46 ` Daniel Henrique Barboza
2024-03-24 15:07 ` Michael Tokarev
2024-03-24 18:12 ` Daniel Henrique Barboza
2024-03-26 9:53 ` Michael Tokarev
2024-03-26 9:56 ` Alistair Francis
2024-03-26 12:09 ` Daniel Henrique Barboza
2024-03-27 10:13 ` Michael Tokarev
2020-06-03 16:13 Alistair Francis
2020-06-04 11:40 ` Peter Maydell
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