[PATCH] arm64: dts: marvell: mcbin: Enable PCIe interface

From: ard.biesheuvel@linaro.org (Ard Biesheuvel)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] arm64: dts: marvell: mcbin: Enable PCIe interface
Date: Thu, 6 Jul 2017 09:39:21 +0100	[thread overview]
Message-ID: <CAKv+Gu-uU7SqcDZdoBfcJHjNMYYVtoH_QfQa7sffcLLOY=iQHQ@mail.gmail.com> (raw)
In-Reply-To: <20170706143151.26e485fa@xhacker>

On 6 July 2017 at 07:31, Jisheng Zhang <jszhang@marvell.com> wrote:
> On Wed, 5 Jul 2017 18:44:03 +0100 Russell King - ARM Linux wrote:
>
>> On Wed, Jul 05, 2017 at 06:36:53PM +0100, Ard Biesheuvel wrote:
>> > On 5 July 2017 at 18:16, Russell King - ARM Linux <linux@armlinux.org.uk> wrote:
>> > > On Wed, Jul 05, 2017 at 06:13:33PM +0200, Gregory CLEMENT wrote:
>> > >> Enable the PCIe interface on the MACCHIATOBin board. It is located on
>> > >> CON12 and is 4 lanes capable.
>> > >>
>> > >> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>> > >
>> > > Why do you folk at free-electrons like doing half a job all the friggin
>> > > time?
>> > >
>> > > You know I have complete patches for mcbin, but you pointedly won't look
>> > > at them at all - except when you have a problem and want to test my tree.
>> > > And even then, you ignore my work (despite testing that it works), and
>> > > you still recreate my patches.
>> > >
>> > > This is really frustrating and insane behaviour on your part.
>> > >
>> > > Here's what I have:
>> > >
>> > > +&cpm_pcie0 {
>> > > +       pinctrl-names = "default";
>> > > +       pinctrl-0 = <&cpm_pcie_pins>;
>> > > +       num-lanes = <4>;
>> > > +       reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>;
>> > > +       status = "okay";
>> >
>> > This needs 'num-viewport = <8>' as well, or the crazy Synopsys DWC
>
> IMHO, maybe putting this property into dtsi is better.
>

Good point. Do all instances of this IP that live on the SoC have 8 viewports?