From: Nick Desaulniers <ndesaulniers@google.com>
To: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Peter Zijlstra <peterz@infradead.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Ard.Biesheuvel@arm.com, andrew.murray@arm.com,
Nathan Chancellor <natechancellor@gmail.com>,
Robin Murphy <robin.murphy@arm.com>,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v5 10/10] arm64: atomics: Use K constraint when toolchain appears to support it
Date: Thu, 29 Aug 2019 10:45:57 -0700 [thread overview]
Message-ID: <CAKwvOdkaCTQ92hUe823Y14xo_Gft4vsRGgimHc8QPUBCbbAOrQ@mail.gmail.com> (raw)
In-Reply-To: <20190829165457.grindfmgpdpsbt4i@willie-the-truck>
On Thu, Aug 29, 2019 at 9:55 AM Will Deacon <will@kernel.org> wrote:
>
> On Thu, Aug 29, 2019 at 04:48:34PM +0100, Will Deacon wrote:
> > diff --git a/arch/arm64/include/asm/atomic_ll_sc.h b/arch/arm64/include/asm/atomic_ll_sc.h
> > index 95091f72228b..7fa042f5444e 100644
> > --- a/arch/arm64/include/asm/atomic_ll_sc.h
> > +++ b/arch/arm64/include/asm/atomic_ll_sc.h
> > @@ -23,6 +23,10 @@ asm_ops "\n" \
> > #define __LL_SC_FALLBACK(asm_ops) asm_ops
> > #endif
> >
> > +#ifndef CONFIG_CC_HAS_K_CONSTRAINT
> > +#define K
> > +#endif
>
> Bah, I need to use something like __stringify when the constraint is used
> in order for this to get expanded properly. Updated diff below.
>
> Will
Hi Will, thanks for cc'ing me on the patch set. I'd be happy to help
test w/ Clang. Would you mind pushing this set with the below diff to
a publicly available tree+branch I can pull from? (I haven't yet
figured out how to download multiple diff's from gmail rather than 1
by 1, and TBH I'd rather just use git).
>
> --->8
>
> diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
> index 61de992bbea3..0cef056b5fb1 100644
> --- a/arch/arm64/Makefile
> +++ b/arch/arm64/Makefile
> @@ -39,6 +39,12 @@ $(warning LSE atomics not supported by binutils)
> endif
> endif
>
> +cc_has_k_constraint := $(call try-run,echo \
> + 'int main(void) { \
> + asm volatile("and w0, w0, %w0" :: "K" (4294967295)); \
> + return 0; \
> + }' | $(CC) -S -x c -o "$$TMP" -,,-DCONFIG_CC_HAS_K_CONSTRAINT=1)
> +
> ifeq ($(CONFIG_ARM64), y)
> brokengasinst := $(call as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n,,-DCONFIG_BROKEN_GAS_INST=1)
>
> @@ -63,7 +69,8 @@ ifeq ($(CONFIG_GENERIC_COMPAT_VDSO), y)
> endif
> endif
>
> -KBUILD_CFLAGS += -mgeneral-regs-only $(lseinstr) $(brokengasinst) $(compat_vdso)
> +KBUILD_CFLAGS += -mgeneral-regs-only $(lseinstr) $(brokengasinst) \
> + $(compat_vdso) $(cc_has_k_constraint)
> KBUILD_CFLAGS += -fno-asynchronous-unwind-tables
> KBUILD_CFLAGS += $(call cc-disable-warning, psabi)
> KBUILD_AFLAGS += $(lseinstr) $(brokengasinst) $(compat_vdso)
> diff --git a/arch/arm64/include/asm/atomic_ll_sc.h b/arch/arm64/include/asm/atomic_ll_sc.h
> index 95091f72228b..7b012148bfd6 100644
> --- a/arch/arm64/include/asm/atomic_ll_sc.h
> +++ b/arch/arm64/include/asm/atomic_ll_sc.h
> @@ -10,6 +10,8 @@
> #ifndef __ASM_ATOMIC_LL_SC_H
> #define __ASM_ATOMIC_LL_SC_H
>
> +#include <linux/stringify.h>
> +
> #if IS_ENABLED(CONFIG_ARM64_LSE_ATOMICS) && IS_ENABLED(CONFIG_AS_LSE)
> #define __LL_SC_FALLBACK(asm_ops) \
> " b 3f\n" \
> @@ -23,6 +25,10 @@ asm_ops "\n" \
> #define __LL_SC_FALLBACK(asm_ops) asm_ops
> #endif
>
> +#ifndef CONFIG_CC_HAS_K_CONSTRAINT
> +#define K
> +#endif
> +
> /*
> * AArch64 UP and SMP safe atomic ops. We use load exclusive and
> * store exclusive to ensure that these are atomic. We may loop
> @@ -44,7 +50,7 @@ __ll_sc_atomic_##op(int i, atomic_t *v) \
> " stxr %w1, %w0, %2\n" \
> " cbnz %w1, 1b\n") \
> : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
> - : #constraint "r" (i)); \
> + : __stringify(constraint) "r" (i)); \
> }
>
> #define ATOMIC_OP_RETURN(name, mb, acq, rel, cl, op, asm_op, constraint)\
> @@ -63,7 +69,7 @@ __ll_sc_atomic_##op##_return##name(int i, atomic_t *v) \
> " cbnz %w1, 1b\n" \
> " " #mb ) \
> : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
> - : #constraint "r" (i) \
> + : __stringify(constraint) "r" (i) \
> : cl); \
> \
> return result; \
> @@ -85,7 +91,7 @@ __ll_sc_atomic_fetch_##op##name(int i, atomic_t *v) \
> " cbnz %w2, 1b\n" \
> " " #mb ) \
> : "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (v->counter) \
> - : #constraint "r" (i) \
> + : __stringify(constraint) "r" (i) \
> : cl); \
> \
> return result; \
> @@ -113,10 +119,15 @@ ATOMIC_OPS(sub, sub, J)
> ATOMIC_FETCH_OP (_acquire, , a, , "memory", __VA_ARGS__)\
> ATOMIC_FETCH_OP (_release, , , l, "memory", __VA_ARGS__)
>
> -ATOMIC_OPS(and, and, )
> +ATOMIC_OPS(and, and, K)
> +ATOMIC_OPS(or, orr, K)
> +ATOMIC_OPS(xor, eor, K)
> +/*
> + * GAS converts the mysterious and undocumented BIC (immediate) alias to
> + * an AND (immediate) instruction with the immediate inverted. We don't
> + * have a constraint for this, so fall back to register.
> + */
> ATOMIC_OPS(andnot, bic, )
> -ATOMIC_OPS(or, orr, )
> -ATOMIC_OPS(xor, eor, )
>
> #undef ATOMIC_OPS
> #undef ATOMIC_FETCH_OP
> @@ -138,7 +149,7 @@ __ll_sc_atomic64_##op(s64 i, atomic64_t *v) \
> " stxr %w1, %0, %2\n" \
> " cbnz %w1, 1b") \
> : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
> - : #constraint "r" (i)); \
> + : __stringify(constraint) "r" (i)); \
> }
>
> #define ATOMIC64_OP_RETURN(name, mb, acq, rel, cl, op, asm_op, constraint)\
> @@ -157,7 +168,7 @@ __ll_sc_atomic64_##op##_return##name(s64 i, atomic64_t *v) \
> " cbnz %w1, 1b\n" \
> " " #mb ) \
> : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
> - : #constraint "r" (i) \
> + : __stringify(constraint) "r" (i) \
> : cl); \
> \
> return result; \
> @@ -179,7 +190,7 @@ __ll_sc_atomic64_fetch_##op##name(s64 i, atomic64_t *v) \
> " cbnz %w2, 1b\n" \
> " " #mb ) \
> : "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (v->counter) \
> - : #constraint "r" (i) \
> + : __stringify(constraint) "r" (i) \
> : cl); \
> \
> return result; \
> @@ -208,9 +219,14 @@ ATOMIC64_OPS(sub, sub, J)
> ATOMIC64_FETCH_OP (_release,, , l, "memory", __VA_ARGS__)
>
> ATOMIC64_OPS(and, and, L)
> -ATOMIC64_OPS(andnot, bic, )
> ATOMIC64_OPS(or, orr, L)
> ATOMIC64_OPS(xor, eor, L)
> +/*
> + * GAS converts the mysterious and undocumented BIC (immediate) alias to
> + * an AND (immediate) instruction with the immediate inverted. We don't
> + * have a constraint for this, so fall back to register.
> + */
> +ATOMIC64_OPS(andnot, bic, )
>
> #undef ATOMIC64_OPS
> #undef ATOMIC64_FETCH_OP
> @@ -269,7 +285,7 @@ __ll_sc__cmpxchg_case_##name##sz(volatile void *ptr, \
> "2:") \
> : [tmp] "=&r" (tmp), [oldval] "=&r" (oldval), \
> [v] "+Q" (*(u##sz *)ptr) \
> - : [old] #constraint "r" (old), [new] "r" (new) \
> + : [old] __stringify(constraint) "r" (old), [new] "r" (new) \
> : cl); \
> \
> return oldval; \
> @@ -280,21 +296,21 @@ __ll_sc__cmpxchg_case_##name##sz(volatile void *ptr, \
> * handle the 'K' constraint for the value 4294967295 - thus we use no
> * constraint for 32 bit operations.
> */
> -__CMPXCHG_CASE(w, b, , 8, , , , , )
> -__CMPXCHG_CASE(w, h, , 16, , , , , )
> -__CMPXCHG_CASE(w, , , 32, , , , , )
> +__CMPXCHG_CASE(w, b, , 8, , , , , K)
> +__CMPXCHG_CASE(w, h, , 16, , , , , K)
> +__CMPXCHG_CASE(w, , , 32, , , , , K)
> __CMPXCHG_CASE( , , , 64, , , , , L)
> -__CMPXCHG_CASE(w, b, acq_, 8, , a, , "memory", )
> -__CMPXCHG_CASE(w, h, acq_, 16, , a, , "memory", )
> -__CMPXCHG_CASE(w, , acq_, 32, , a, , "memory", )
> +__CMPXCHG_CASE(w, b, acq_, 8, , a, , "memory", K)
> +__CMPXCHG_CASE(w, h, acq_, 16, , a, , "memory", K)
> +__CMPXCHG_CASE(w, , acq_, 32, , a, , "memory", K)
> __CMPXCHG_CASE( , , acq_, 64, , a, , "memory", L)
> -__CMPXCHG_CASE(w, b, rel_, 8, , , l, "memory", )
> -__CMPXCHG_CASE(w, h, rel_, 16, , , l, "memory", )
> -__CMPXCHG_CASE(w, , rel_, 32, , , l, "memory", )
> +__CMPXCHG_CASE(w, b, rel_, 8, , , l, "memory", K)
> +__CMPXCHG_CASE(w, h, rel_, 16, , , l, "memory", K)
> +__CMPXCHG_CASE(w, , rel_, 32, , , l, "memory", K)
> __CMPXCHG_CASE( , , rel_, 64, , , l, "memory", L)
> -__CMPXCHG_CASE(w, b, mb_, 8, dmb ish, , l, "memory", )
> -__CMPXCHG_CASE(w, h, mb_, 16, dmb ish, , l, "memory", )
> -__CMPXCHG_CASE(w, , mb_, 32, dmb ish, , l, "memory", )
> +__CMPXCHG_CASE(w, b, mb_, 8, dmb ish, , l, "memory", K)
> +__CMPXCHG_CASE(w, h, mb_, 16, dmb ish, , l, "memory", K)
> +__CMPXCHG_CASE(w, , mb_, 32, dmb ish, , l, "memory", K)
> __CMPXCHG_CASE( , , mb_, 64, dmb ish, , l, "memory", L)
>
> #undef __CMPXCHG_CASE
> @@ -332,5 +348,6 @@ __CMPXCHG_DBL( , , , )
> __CMPXCHG_DBL(_mb, dmb ish, l, "memory")
>
> #undef __CMPXCHG_DBL
> +#undef K
>
> #endif /* __ASM_ATOMIC_LL_SC_H */
--
Thanks,
~Nick Desaulniers
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next prev parent reply other threads:[~2019-08-29 17:46 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-29 15:48 [PATCH v5 00/10] arm64: avoid out-of-line ll/sc atomics Will Deacon
2019-08-29 15:48 ` [PATCH v5 01/10] jump_label: Don't warn on __exit jump entries Will Deacon
2019-08-29 15:48 ` [PATCH v5 02/10] arm64: Use correct ll/sc atomic constraints Will Deacon
2019-08-29 15:48 ` [PATCH v5 03/10] arm64: atomics: avoid out-of-line ll/sc atomics Will Deacon
2019-09-03 6:00 ` Nathan Chancellor
2019-09-03 6:39 ` Will Deacon
2019-09-03 14:31 ` Andrew Murray
2019-09-03 14:45 ` Will Deacon
2019-09-03 15:15 ` Andrew Murray
2019-09-03 15:31 ` Andrew Murray
2019-09-03 16:37 ` Will Deacon
2019-09-03 22:04 ` Andrew Murray
2019-09-03 22:35 ` Nick Desaulniers
[not found] ` <CANW9uyuRFtNKMnSwmHWt_RebJA1ADXdZfeDHc6=yaaFH2NsyWg@mail.gmail.com>
2019-09-03 22:53 ` Nick Desaulniers
2019-09-04 10:20 ` Will Deacon
2019-09-04 17:28 ` Nick Desaulniers
2019-09-05 11:25 ` Andrew Murray
2019-09-06 19:44 ` Nick Desaulniers
2019-08-29 15:48 ` [PATCH v5 04/10] arm64: avoid using hard-coded registers for LSE atomics Will Deacon
2019-08-29 15:48 ` [PATCH v5 05/10] arm64: atomics: Remove atomic_ll_sc compilation unit Will Deacon
2019-08-29 17:47 ` Nick Desaulniers
2019-08-29 20:07 ` Tri Vo
2019-08-29 21:54 ` Will Deacon
2019-08-29 15:48 ` [PATCH v5 06/10] arm64: lse: Remove unused 'alt_lse' assembly macro Will Deacon
2019-08-29 23:39 ` Andrew Murray
2019-08-29 15:48 ` [PATCH v5 07/10] arm64: asm: Kill 'asm/atomic_arch.h' Will Deacon
2019-08-29 23:43 ` Andrew Murray
2019-08-29 15:48 ` [PATCH v5 08/10] arm64: lse: Make ARM64_LSE_ATOMICS depend on JUMP_LABEL Will Deacon
2019-08-29 23:44 ` Andrew Murray
2019-08-29 15:48 ` [PATCH v5 09/10] arm64: atomics: Undefine internal macros after use Will Deacon
2019-08-29 23:44 ` Andrew Murray
2019-08-29 15:48 ` [PATCH v5 10/10] arm64: atomics: Use K constraint when toolchain appears to support it Will Deacon
2019-08-29 16:54 ` Will Deacon
2019-08-29 17:45 ` Nick Desaulniers [this message]
2019-08-29 21:53 ` Will Deacon
2019-08-30 20:57 ` Nick Desaulniers
2019-08-30 0:08 ` Andrew Murray
2019-08-30 7:52 ` Will Deacon
2019-08-30 9:11 ` Andrew Murray
2019-08-30 10:17 ` Will Deacon
2019-08-30 11:57 ` Andrew Murray
2019-08-30 10:40 ` Mark Rutland
2019-08-30 11:53 ` Andrew Murray
2019-08-29 23:49 ` Andrew Murray
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