From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: Greg Ungerer <gerg@kernel.org>
Cc: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>,
linux-kernel <linux-kernel@vger.kernel.org>,
"open list:MIPS" <linux-mips@vger.kernel.org>,
liwei391@huawei.com, macro@orcam.me.uk, nbd@nbd.name,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
yangtiezhu@loongson.cn
Subject: Re: [PATCH v3] MIPS: add support for buggy MT7621S core detection
Date: Thu, 16 Sep 2021 08:33:28 +0200 [thread overview]
Message-ID: <CAMhs-H-_6fH00g4tkF7KBgO_HvA1c6QVV8ph2gSXFaoVUAZRUQ@mail.gmail.com> (raw)
In-Reply-To: <4d9e3b39-7caa-d372-5d7b-42dcec36fec7@kernel.org>
Hi Greg,
On Thu, Sep 16, 2021 at 4:57 AM Greg Ungerer <gerg@kernel.org> wrote:
>
> Hi Ilya,
>
> > Most MT7621 SoCs have 2 cores, which is detected and supported properly
> > by CPS.
> >
> > Unfortunately, MT7621 SoC has a less common S variant with only one core.
> > On MT7621S, GCR_CONFIG still reports 2 cores, which leads to hangs when
> > starting SMP. CPULAUNCH registers can be used in that case to detect the
> > absence of the second core and override the GCR_CONFIG PCORES field.
> >
> > Rework a long-standing OpenWrt patch to override the value of
> > mips_cps_numcores on single-core MT7621 systems.
> >
> > Tested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core
> > MT7621 device (Netgear R6220).
>
> This is breaking core detection on my MT7621 based platforms.
> I only get 2 cores detected now running 5.13. Reverting this change gives
> me 4 cores back.
I also have a 4 core mt7621 based board and this patch change does not
have problems for me. Let me know if you need me to check something
from my board.
I noticed that on boot the following message appears and might be
related with the way used here to make the core number detection:
[ 0.000000] VPE topology {2,2} total 4
Is this the same for your board?
Best regards,
Sergio Paracuellos
>
> From a fully working (pre-change) system I get:
>
> # cat /proc/cpuinfo
> system type : MediaTek MT7621 ver:1 eco:3
> machine : Digi EX15
> processor : 0
> cpu model : MIPS 1004Kc V2.15
> BogoMIPS : 586.13
> wait instruction : yes
> microsecond timers : yes
> tlb_entries : 32
> extra interrupt vector : yes
> hardware watchpoint : yes, count: 4, address/irw mask: [0x0ffc, 0x0ffc, 0x0ffb, 0x0ffb]
> isa : mips1 mips2 mips32r1 mips32r2
> ASEs implemented : mips16 dsp mt
> shadow register sets : 1
> kscratch registers : 0
> package : 0
> core : 0
> VPE : 0
> VCED exceptions : not available
> VCEI exceptions : not available
>
> processor : 1
> cpu model : MIPS 1004Kc V2.15
> BogoMIPS : 586.13
> wait instruction : yes
> microsecond timers : yes
> tlb_entries : 32
> extra interrupt vector : yes
> hardware watchpoint : yes, count: 4, address/irw mask: [0x0ffc, 0x0ffc, 0x0ffb, 0x0ffb]
> isa : mips1 mips2 mips32r1 mips32r2
> ASEs implemented : mips16 dsp mt
> shadow register sets : 1
> kscratch registers : 0
> package : 0
> core : 0
> VPE : 1
> VCED exceptions : not available
> VCEI exceptions : not available
>
> processor : 2
> cpu model : MIPS 1004Kc V2.15
> BogoMIPS : 586.13
> wait instruction : yes
> microsecond timers : yes
> tlb_entries : 32
> extra interrupt vector : yes
> hardware watchpoint : yes, count: 4, address/irw mask: [0x0ffc, 0x0ffc, 0x0ffb, 0x0ffb]
> isa : mips1 mips2 mips32r1 mips32r2
> ASEs implemented : mips16 dsp mt
> shadow register sets : 1
> kscratch registers : 0
> package : 0
> core : 1
> VPE : 0
> VCED exceptions : not available
> VCEI exceptions : not available
>
> processor : 3
> cpu model : MIPS 1004Kc V2.15
> BogoMIPS : 586.13
> wait instruction : yes
> microsecond timers : yes
> tlb_entries : 32
> extra interrupt vector : yes
> hardware watchpoint : yes, count: 4, address/irw mask: [0x0ffc, 0x0ffc, 0x0ffb, 0x0ffb]
> isa : mips1 mips2 mips32r1 mips32r2
> ASEs implemented : mips16 dsp mt
> shadow register sets : 1
> kscratch registers : 0
> package : 0
> core : 1
> VPE : 1
> VCED exceptions : not available
> VCEI exceptions : not available
>
>
> After this patch is applied:
>
> # cat /proc/cpuinfo
> system type : MediaTek MT7621 ver:1 eco:3
> machine : Digi EX15
> processor : 0
> cpu model : MIPS 1004Kc V2.15
> BogoMIPS : 586.13
> wait instruction : yes
> microsecond timers : yes
> tlb_entries : 32
> extra interrupt vector : yes
> hardware watchpoint : yes, count: 4, address/irw mask: [0x0ffc, 0x0ffc, 0x0ffb, 0x0ffb]
> isa : mips1 mips2 mips32r1 mips32r2
> ASEs implemented : mips16 dsp mt
> shadow register sets : 1
> kscratch registers : 0
> package : 0
> core : 0
> VPE : 0
> VCED exceptions : not available
> VCEI exceptions : not available
>
> processor : 1
> cpu model : MIPS 1004Kc V2.15
> BogoMIPS : 586.13
> wait instruction : yes
> microsecond timers : yes
> tlb_entries : 32
> extra interrupt vector : yes
> hardware watchpoint : yes, count: 4, address/irw mask: [0x0ffc, 0x0ffc, 0x0ffb, 0x0ffb]
> isa : mips1 mips2 mips32r1 mips32r2
> ASEs implemented : mips16 dsp mt
> shadow register sets : 1
> kscratch registers : 0
> package : 0
> core : 0
> VPE : 1
> VCED exceptions : not available
> VCEI exceptions : not available
>
> Any ideas?
>
> Regards
> Greg
>
>
> > Original 4.14 OpenWrt patch:
> > Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=4cdbc90a376dd0555201c1434a2081e055e9ceb7
> > Current 5.10 OpenWrt patch:
> > Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch;h=c63f0f4c1ec742e24d8480e80553863744b58f6a;hb=10267e17299806f9885d086147878f6c492cb904
> >
> > Suggested-by: Felix Fietkau <nbd@nbd.name>
> > Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
> > ---
> > arch/mips/include/asm/mips-cps.h | 23 ++++++++++++++++++++++-
> > 1 file changed, 22 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/mips/include/asm/mips-cps.h b/arch/mips/include/asm/mips-cps.h
> > index fd43d876892e..35fb8ee6dd33 100644
> > --- a/arch/mips/include/asm/mips-cps.h
> > +++ b/arch/mips/include/asm/mips-cps.h
> > @@ -10,6 +10,8 @@
> > #include <linux/io.h>
> > #include <linux/types.h>
> >
> > +#include <asm/mips-boards/launch.h>
> > +
> > extern unsigned long __cps_access_bad_size(void)
> > __compiletime_error("Bad size for CPS accessor");
> >
> > @@ -165,11 +167,30 @@ static inline uint64_t mips_cps_cluster_config(unsigned int cluster)
> > */
> > static inline unsigned int mips_cps_numcores(unsigned int cluster)
> > {
> > + unsigned int ncores;
> > +
> > if (!mips_cm_present())
> > return 0;
> >
> > /* Add one before masking to handle 0xff indicating no cores */
> > - return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
> > + ncores = (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
> > +
> > + if (IS_ENABLED(CONFIG_SOC_MT7621)) {
> > + struct cpulaunch *launch;
> > +
> > + /*
> > + * Ralink MT7621S SoC is single core, but the GCR_CONFIG method
> > + * always reports 2 cores. Check the second core's LAUNCH_FREADY
> > + * flag to detect if the second core is missing. This method
> > + * only works before the core has been started.
> > + */
> > + launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
> > + launch += 2; /* MT7621 has 2 VPEs per core */
> > + if (!(launch->flags & LAUNCH_FREADY))
> > + ncores = 1;
> > + }
> > +
> > + return ncores;
> > }
> >
> > /**
> > --
> > 2.31.1
>
next prev parent reply other threads:[~2021-09-16 6:33 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-16 2:56 [PATCH v3] MIPS: add support for buggy MT7621S core detection Greg Ungerer
2021-09-16 6:33 ` Sergio Paracuellos [this message]
2021-09-16 6:54 ` Greg Ungerer
2021-09-16 8:54 ` Strontium
2021-09-30 12:41 ` Greg Ungerer
2021-09-30 13:35 ` Sergio Paracuellos
2021-09-30 16:41 ` Ilya Lipnitskiy
2021-09-30 22:36 ` Greg Ungerer
[not found] ` <d1eb4cb4-6e9e-3f3c-8ca7-a84d03bb9f53@gmail.com>
2021-10-01 5:04 ` Sergio Paracuellos
-- strict thread matches above, loose matches on Subject: below --
2021-04-07 13:52 [PATCH v2] " Maciej W. Rozycki
2021-04-07 20:07 ` [PATCH v3] " Ilya Lipnitskiy
2021-04-12 15:03 ` Thomas Bogendoerfer
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAMhs-H-_6fH00g4tkF7KBgO_HvA1c6QVV8ph2gSXFaoVUAZRUQ@mail.gmail.com \
--to=sergio.paracuellos@gmail.com \
--cc=gerg@kernel.org \
--cc=ilya.lipnitskiy@gmail.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mips@vger.kernel.org \
--cc=liwei391@huawei.com \
--cc=macro@orcam.me.uk \
--cc=nbd@nbd.name \
--cc=tsbogend@alpha.franken.de \
--cc=yangtiezhu@loongson.cn \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.