Re: [PATCH 15/17] m68k: Implement the new page table range API

From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Matthew Wilcox <willy@infradead.org>
Cc: Michael Schmitz <schmitzmic@gmail.com>,
	linux-mm@kvack.org, linux-m68k@lists.linux-m68k.org,
	linux-arch@vger.kernel.org
Subject: Re: [PATCH 15/17] m68k: Implement the new page table range API
Date: Thu, 16 Feb 2023 08:55:27 +0100	[thread overview]
Message-ID: <CAMuHMdUtjetsA8_cZAmyTR07CD5SbyV8aSymjd4wL5+TgW2Jgg@mail.gmail.com> (raw)
In-Reply-To: <Y+2wdSxVgS6HmFRy@casper.infradead.org>

Hi Matthew,

On Thu, Feb 16, 2023 at 5:26 AM Matthew Wilcox <willy@infradead.org> wrote:
> On Thu, Feb 16, 2023 at 01:59:44PM +1300, Michael Schmitz wrote:
> > On 16/02/23 09:09, Matthew Wilcox (Oracle) wrote:
> > > Add set_ptes(), update_mmu_cache_range(), flush_icache_pages() and
> > > flush_dcache_folio().  I'm not entirely certain that the 040/060 case
> > > in __flush_pages_to_ram() is correct.
> >
> > I'm pretty sure you need to iterate to hit each of the pages - the code as
> > is will only push cache entries for the first page.
> >
> > Quoting the 040 UM:
> >
> > "Both instructions [cinv, cpush] allow operation on a single cache line, all
> > cache lines in a specific page, or an entire cache, and can select one or
> > both caches for the operation. For line and page operations, a physical
> > address in an address register specifies the memory address."
>
> I actually found that!  What I didn't find was how to tell if this
> cpush insn is the one which is operating on a single cache line,
> a single page, or the entire cache.

cpushl (line), cpushp (page), cpusha (all).
Same for cinv.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds