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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Cc: Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	Wolfram Sang <wsa@the-dreams.de>,
	"linux-serial@vger.kernel.org" <linux-serial@vger.kernel.org>,
	Magnus Damm <magnus.damm@gmail.com>
Subject: Re: [PATCH 5/7] serial: sh-sci: SCIFA/B RX FIFO software timeout
Date: Wed, 14 Dec 2016 15:02:28 +0100	[thread overview]
Message-ID: <CAMuHMdWmCgiAH3hnAQJVxhz70bLOMccsWOR1gmSmbKeEwW_Fgg@mail.gmail.com> (raw)
In-Reply-To: <1481286971-16667-6-git-send-email-ulrich.hecht+renesas@gmail.com>

Hi Uli.

On Fri, Dec 9, 2016 at 1:36 PM, Ulrich Hecht
<ulrich.hecht+renesas@gmail.com> wrote:
> Implements support for FIFO fill thresholds greater than one with software
> timeout.
>
> This mechanism is not possible (or at least not useful) on SCIF family
> hardware other than SCIFA and SCIFB because they do not support turning off
> the DR hardware timeout interrupt separately from the RI interrupt.

What about HSCIF? Your code does handle HSCIF (cfr. HSRTRGR below)?

> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c

> @@ -1159,6 +1162,24 @@ static int scif_set_rtrg(struct uart_port *port, int rx_trig)
>         return rx_trig;
>  }
>
> +static int scif_rtrg_enabled(struct uart_port *port)
> +{
> +       if (sci_getreg(port, HSRTRGR)->size)
> +               return serial_port_in(port, HSRTRGR) != 0;
> +       else
> +               return (serial_port_in(port, SCFCR) &
> +                       (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
> +}

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

  reply	other threads:[~2016-12-14 14:17 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-12-09 12:36 [PATCH 0/7] Renesas *SCIF* RX FIFO support Ulrich Hecht
2016-12-09 12:36 ` [PATCH 1/7] serial: sh-sci: add FIFO trigger bits Ulrich Hecht
2016-12-14 13:35   ` Geert Uytterhoeven
2016-12-09 12:36 ` [PATCH 2/7] serial: sh-sci: consider DR (data ready) bit adequately Ulrich Hecht
2016-12-14 13:45   ` Geert Uytterhoeven
2016-12-09 12:36 ` [PATCH 3/7] serial: sh-sci: implement FIFO threshold register setting Ulrich Hecht
2016-12-12 10:21   ` Sergei Shtylyov
2016-12-14 13:50   ` Geert Uytterhoeven
2016-12-09 12:36 ` [PATCH 4/7] serial: sh-sci: increase RX FIFO trigger defaults for (H)SCIF Ulrich Hecht
2016-12-14 13:58   ` Geert Uytterhoeven
2016-12-09 12:36 ` [PATCH 5/7] serial: sh-sci: SCIFA/B RX FIFO software timeout Ulrich Hecht
2016-12-14 14:02   ` Geert Uytterhoeven [this message]
2017-01-23 16:04     ` Ulrich Hecht
2016-12-09 12:36 ` [PATCH 6/7] serial: sh-sci: make RX FIFO parameters tunable via sysfs Ulrich Hecht
2016-12-14 14:04   ` Geert Uytterhoeven
2016-12-09 12:36 ` [PATCH 7/7] arm64: dts: r8a7796: salvator-x: add SCIF1 (DEBUG1) Ulrich Hecht
2016-12-14 14:10   ` Geert Uytterhoeven

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