RE: [PATCH v2] drm/i915: Reuse RPLU cdclk fns for MTL+

From: "Sripada, Radhakrishna" <radhakrishna.sripada@intel.com>
To: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Cc: "Sousa, Gustavo" <gustavo.sousa@intel.com>,
	"Nikula, Jani" <jani.nikula@intel.com>
Subject: RE: [PATCH v2] drm/i915: Reuse RPLU cdclk fns for MTL+
Date: Mon, 11 Mar 2024 17:58:02 +0000	[thread overview]
Message-ID: <DM4PR11MB597120463B925ACB63BAA67687242@DM4PR11MB5971.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20240228214854.2530205-1-radhakrishna.sripada@intel.com>

Merged the patch. Thanks for the reviews.

Regards,
Radhakrishna Sripada

> -----Original Message-----
> From: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Sent: Wednesday, February 28, 2024 1:49 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; Sousa, Gustavo
> <gustavo.sousa@intel.com>; Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH v2] drm/i915: Reuse RPLU cdclk fns for MTL+
> 
> MTL/LNL use the same cdclk functions as RPLU albeit with different
> tables. Having separate tables and not requiring special handling
> for the platforms, reuse RPLU cdclk functions.
> 
> v2: Update subject and the commit message(Jani)
> 
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 11 ++---------
>  1 file changed, 2 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 22473c55b899..5b2688d8c644 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -3559,13 +3559,6 @@ void intel_cdclk_debugfs_register(struct
> drm_i915_private *i915)
>  			    i915, &i915_cdclk_info_fops);
>  }
> 
> -static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
> -	.get_cdclk = bxt_get_cdclk,
> -	.set_cdclk = bxt_set_cdclk,
> -	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
> -	.calc_voltage_level = rplu_calc_voltage_level,
> -};
> -
>  static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
>  	.get_cdclk = bxt_get_cdclk,
>  	.set_cdclk = bxt_set_cdclk,
> @@ -3709,10 +3702,10 @@ static const struct intel_cdclk_funcs
> i830_cdclk_funcs = {
>  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  {
>  	if (DISPLAY_VER(dev_priv) >= 20) {
> -		dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
> +		dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
>  		dev_priv->display.cdclk.table = lnl_cdclk_table;
>  	} else if (DISPLAY_VER(dev_priv) >= 14) {
> -		dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
> +		dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
>  		dev_priv->display.cdclk.table = mtl_cdclk_table;
>  	} else if (IS_DG2(dev_priv)) {
>  		dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> --
> 2.34.1