RE: [patch net-next 1/3] dpll: expose fractional frequency offset value to user

From: "Kubalewski, Arkadiusz" <arkadiusz.kubalewski@intel.com>
To: Jiri Pirko <jiri@resnulli.us>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>
Cc: "kuba@kernel.org" <kuba@kernel.org>,
	"pabeni@redhat.com" <pabeni@redhat.com>,
	"davem@davemloft.net" <davem@davemloft.net>,
	"edumazet@google.com" <edumazet@google.com>,
	"vadim.fedorenko@linux.dev" <vadim.fedorenko@linux.dev>,
	"M, Saeed" <saeedm@nvidia.com>,
	"leon@kernel.org" <leon@kernel.org>,
	"Michalik, Michal" <michal.michalik@intel.com>,
	"rrameshbabu@nvidia.com" <rrameshbabu@nvidia.com>
Subject: RE: [patch net-next 1/3] dpll: expose fractional frequency offset value to user
Date: Fri, 5 Jan 2024 13:32:00 +0000	[thread overview]
Message-ID: <DM6PR11MB46575D0FFEE161D2C32D26C99B662@DM6PR11MB4657.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20240103132838.1501801-2-jiri@resnulli.us>

>From: Jiri Pirko <jiri@resnulli.us>
>Sent: Wednesday, January 3, 2024 2:29 PM
>
>From: Jiri Pirko <jiri@nvidia.com>
>
>Add a new netlink attribute to expose fractional frequency offset value
>for a pin. Add an op to get the value from the driver.
>
>Signed-off-by: Jiri Pirko <jiri@nvidia.com>
>---
> Documentation/netlink/specs/dpll.yaml | 11 +++++++++++
> drivers/dpll/dpll_netlink.c           | 24 ++++++++++++++++++++++++
> include/linux/dpll.h                  |  3 +++
> include/uapi/linux/dpll.h             |  1 +
> 4 files changed, 39 insertions(+)
>
>diff --git a/Documentation/netlink/specs/dpll.yaml
>b/Documentation/netlink/specs/dpll.yaml
>index cf8abe1c0550..b14aed18065f 100644
>--- a/Documentation/netlink/specs/dpll.yaml
>+++ b/Documentation/netlink/specs/dpll.yaml
>@@ -296,6 +296,16 @@ attribute-sets:
>       -
>         name: phase-offset
>         type: s64
>+      -
>+        name: fractional-frequency-offset
>+        type: sint
>+        doc: |
>+          The FFO (Fractional Frequency Offset) between the RX and TX
>+          symbol rate on the media associated with the pin:
>+          (rx_frequency-tx_frequency)/rx_frequency
>+          Value is in PPM (parts per million).
>+          This may be implemented for example for pin of type
>+          PIN_TYPE_SYNCE_ETH_PORT.
>   -
>     name: pin-parent-device
>     subset-of: pin
>@@ -460,6 +470,7 @@ operations:
>             - phase-adjust-min
>             - phase-adjust-max
>             - phase-adjust
>+            - fractional-frequency-offset
>
>       dump:
>         pre: dpll-lock-dumpit
>diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
>index 21c627e9401a..3370dbddb86b 100644
>--- a/drivers/dpll/dpll_netlink.c
>+++ b/drivers/dpll/dpll_netlink.c
>@@ -263,6 +263,27 @@ dpll_msg_add_phase_offset(struct sk_buff *msg, struct
>dpll_pin *pin,
> 	return 0;
> }
>
>+static int dpll_msg_add_ffo(struct sk_buff *msg, struct dpll_pin *pin,
>+			    struct dpll_pin_ref *ref,
>+			    struct netlink_ext_ack *extack)
>+{
>+	const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>+	struct dpll_device *dpll = ref->dpll;
>+	s64 ffo;
>+	int ret;
>+
>+	if (!ops->ffo_get)
>+		return 0;
>+	ret = ops->ffo_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
>+			   dpll, dpll_priv(dpll), &ffo, extack);
>+	if (ret) {
>+		if (ret == -ENODATA)
>+			return 0;
>+		return ret;
>+	}
>+	return nla_put_sint(msg, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET,
>ffo);
>+}
>+
> static int
> dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,
> 		      struct dpll_pin_ref *ref, struct netlink_ext_ack *extack)
>@@ -440,6 +461,9 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct
>dpll_pin *pin,
> 			prop->phase_range.max))
> 		return -EMSGSIZE;
> 	ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);
>+	if (ret)
>+		return ret;
>+	ret = dpll_msg_add_ffo(msg, pin, ref, extack);
> 	if (ret)
> 		return ret;
> 	if (xa_empty(&pin->parent_refs))
>diff --git a/include/linux/dpll.h b/include/linux/dpll.h
>index b1a5f9ca8ee5..9cf896ea1d41 100644
>--- a/include/linux/dpll.h
>+++ b/include/linux/dpll.h
>@@ -77,6 +77,9 @@ struct dpll_pin_ops {
> 				const struct dpll_device *dpll, void *dpll_priv,
> 				const s32 phase_adjust,
> 				struct netlink_ext_ack *extack);
>+	int (*ffo_get)(const struct dpll_pin *pin, void *pin_priv,
>+		       const struct dpll_device *dpll, void *dpll_priv,
>+		       s64 *ffo, struct netlink_ext_ack *extack);
> };
>
> struct dpll_pin_frequency {
>diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h
>index 715a491d2727..b4e947f9bfbc 100644
>--- a/include/uapi/linux/dpll.h
>+++ b/include/uapi/linux/dpll.h
>@@ -179,6 +179,7 @@ enum dpll_a_pin {
> 	DPLL_A_PIN_PHASE_ADJUST_MAX,
> 	DPLL_A_PIN_PHASE_ADJUST,
> 	DPLL_A_PIN_PHASE_OFFSET,
>+	DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET,
>
> 	__DPLL_A_PIN_MAX,
> 	DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)
>--
>2.43.0

Hi Jiri,

In general looks good.

But one thing, there is no update to Documentation/driver-api/dpll.rst
Why not mention this new netlink attribute and some explanation for the
userspace in the non-source-code documentation?

Thanks!
Arkadiusz