From: "Kahola, Mika" <mika.kahola@intel.com>
To: "Sousa, Gustavo" <gustavo.sousa@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Cc: "Nikula, Jani" <jani.nikula@intel.com>
Subject: Re: [Intel-gfx] [PATCH v2 14/21] drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll
Date: Tue, 21 Feb 2023 13:23:24 +0000 [thread overview]
Message-ID: <MW4PR11MB70540F5A1FA435205176CB45EFA59@MW4PR11MB7054.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20230207165552.zzu7f3zj3l7pvgqj@gjsousa-mobl2>
> -----Original Message-----
> From: Sousa, Gustavo <gustavo.sousa@intel.com>
> Sent: Tuesday, February 7, 2023 6:56 PM
> To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v2 14/21] drm/i915/mtl: Enabling/disabling
> sequence Thunderbolt pll
>
> On Thu, Jan 05, 2023 at 02:54:39PM +0200, Mika Kahola wrote:
> > Enabling and disabling sequence for Thunderbolt PLL.
> >
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > Link:
> > https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-15
> > -mika.kahola@intel.com
> > ---
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 137 ++++++++++++++++++-
> > drivers/gpu/drm/i915/display/intel_cx0_phy.h | 7 +-
> > drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
> > 3 files changed, 139 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index 67e8889aec29..9218f99bca4e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -14,8 +14,8 @@
> > #include "intel_hdmi.h"
> > #include "intel_panel.h"
> > #include "intel_psr.h"
> > -#include "intel_uncore.h"
> > #include "intel_tc.h"
> > +#include "intel_uncore.h"
> >
> > bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
> > { @@ -2365,8 +2365,8 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane)
> > XELPDP_LANE1_PCLK_PLL_ACK;
> > }
> >
> > -void intel_cx0pll_enable(struct intel_encoder *encoder,
> > - const struct intel_crtc_state *crtc_state)
> > +static void intel_cx0pll_enable(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state)
> > {
> > struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > enum phy phy = intel_port_to_phy(i915, encoder->port); @@ -2439,7
> > +2439,86 @@ void intel_cx0pll_enable(struct intel_encoder *encoder,
> > intel_cx0_phy_transaction_end(encoder, wakeref); }
> >
> > -void intel_cx0pll_disable(struct intel_encoder *encoder)
> > +static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915,
> > +int clock) {
> > + switch (clock) {
> > + case 162000:
> > + return XELPDP_DDI_CLOCK_SELECT_TBT_162;
> > + case 270000:
> > + return XELPDP_DDI_CLOCK_SELECT_TBT_270;
> > + case 540000:
> > + return XELPDP_DDI_CLOCK_SELECT_TBT_540;
> > + case 810000:
> > + return XELPDP_DDI_CLOCK_SELECT_TBT_810;
> > + default:
> > + MISSING_CASE(clock);
> > + return XELPDP_DDI_CLOCK_SELECT_TBT_162;
> > + }
> > +}
> > +
> > +static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state) {
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > + u32 val = 0;
> > +
> > + /*
> > + * 1. Program PORT_CLOCK_CTL REGISTER to configure
> > + * clock muxes, gating and SSC
> > + */
> > + val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915,
> crtc_state->port_clock));
> > + val |= XELPDP_FORWARD_CLOCK_UNGATE;
> > + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> > + XELPDP_DDI_CLOCK_SELECT_MASK |
> XELPDP_FORWARD_CLOCK_UNGATE,
> > +val);
> > +
> > + /* 2. Read back PORT_CLOCK_CTL REGISTER */
> > + val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
> > +
> > + /*
> > + * 3. Follow the Display Voltage Frequency Switching - Sequence
> > + * Before Frequency Change. We handle this step in bxt_set_cdclk().
> > + */
> > +
> > + /*
> > + * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable
> PLL.
> > + */
> > + val |= XELPDP_TBT_CLOCK_REQUEST;
> > + intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), val);
> > +
> > + /* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
> > + if (__intel_wait_for_register(&i915->uncore,
> XELPDP_PORT_CLOCK_CTL(encoder->port),
> > + XELPDP_TBT_CLOCK_ACK,
> > + XELPDP_TBT_CLOCK_ACK,
> > + 100, 0, NULL))
> > + drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not
> locked after 100us.\n",
> > + encoder->base.base.id, encoder->base.name,
> phy_name(phy));
> > +
> > + /*
> > + * 6. Follow the Display Voltage Frequency Switching Sequence After
> > + * Frequency Change. We handle this step in bxt_set_cdclk().
> > + */
> > +
> > + /*
> > + * 7. Program DDI_CLK_VALFREQ to match intended DDI
> > + * clock frequency.
> > + */
> > + intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
> > + crtc_state->port_clock);
> > +}
> > +
> > +void intel_mtl_pll_enable(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state) {
> > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > +
> > + if (intel_tc_port_in_tbt_alt_mode(dig_port))
> > + intel_mtl_tbt_pll_enable(encoder, crtc_state);
> > + else
> > + intel_cx0pll_enable(encoder, crtc_state); }
> > +
> > +static void intel_cx0pll_disable(struct intel_encoder *encoder)
> > {
> > struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > enum phy phy = intel_port_to_phy(i915, encoder->port); @@ -2491,6
> > +2570,56 @@ void intel_cx0pll_disable(struct intel_encoder *encoder)
> > intel_cx0_phy_transaction_end(encoder, wakeref); }
> >
> > +static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
> > +{
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > +
> > + /*
> > + * 1. Follow the Display Voltage Frequency Switching Sequence Before
> > + * Frequency Change. We handle this step in bxt_set_cdclk().
> > + */
> > +
> > + /*
> > + * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable
> PLL.
> > + */
> > + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> > + XELPDP_TBT_CLOCK_REQUEST, 0);
> > +
> > + /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
> > + if (__intel_wait_for_register(&i915->uncore,
> XELPDP_PORT_CLOCK_CTL(encoder->port),
> > + XELPDP_TBT_CLOCK_ACK,
> > + ~XELPDP_TBT_CLOCK_ACK,
>
> I think we can just use 0 instead of ~XELPDP_TBT_CLOCK_ACK.
Yes we could use just '0' here.
>
> > + 10, 0, NULL))
> > + drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not
> unlocked after 10us.\n",
> > + encoder->base.base.id, encoder->base.name,
> phy_name(phy));
> > +
> > + /*
> > + * 4. Follow the Display Voltage Frequency Switching Sequence After
> > + * Frequency Change. We handle this step in bxt_set_cdclk().
> > + */
> > +
> > + /*
> > + * 5. Program PORT CLOCK CTRL register to disable and gate clocks
> > + */
> > + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> > + XELPDP_DDI_CLOCK_SELECT_MASK |
> > + XELPDP_FORWARD_CLOCK_UNGATE, 0);
> > +
> > + /* 6. Program DDI_CLK_VALFREQ to 0. */
> > + intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0); }
> > +
> > +void intel_mtl_pll_disable(struct intel_encoder *encoder) {
> > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > +
> > + if (intel_tc_port_in_tbt_alt_mode(dig_port))
> > + intel_mtl_tbt_pll_disable(encoder);
> > + else
> > + intel_cx0pll_disable(encoder);
> > +}
> > +
> > void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
> > struct intel_crtc_state *new_crtc_state) { diff
> --git
> > a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > index 8ca77dfea24b..141802038f12 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > @@ -26,9 +26,9 @@ enum phy;
> > #define MB_WRITE_UNCOMMITTED 0
> >
> > bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy
> > phy); -void intel_cx0pll_enable(struct intel_encoder *encoder,
> > - const struct intel_crtc_state *crtc_state);
> > -void intel_cx0pll_disable(struct intel_encoder *encoder);
> > +void intel_mtl_pll_enable(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state); void
> > +intel_mtl_pll_disable(struct intel_encoder *encoder);
> > void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
> > struct intel_c10mpllb_state *pll_state); int
> > intel_cx0mpllb_calc_state(struct intel_crtc_state *crtc_state, @@
> > -53,4 +53,5 @@ int intel_c20_phy_check_hdmi_link_rate(int clock);
> > void intel_cx0_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state,
> > u32 level);
> > +int intel_mtl_tbt_readout_hw_state(struct intel_encoder *encoder);
> > #endif /* __INTEL_CX0_PHY_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 829c90b17b08..c2b9a2053732 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4419,8 +4419,8 @@ void intel_ddi_init(struct drm_i915_private
> *dev_priv, enum port port)
> > encoder->pipe_mask = ~0;
> >
> > if (DISPLAY_VER(dev_priv) >= 14) {
> > - encoder->enable_clock = intel_cx0pll_enable;
> > - encoder->disable_clock = intel_cx0pll_disable;
> > + encoder->enable_clock = intel_mtl_pll_enable;
> > + encoder->disable_clock = intel_mtl_pll_disable;
> > encoder->get_config = mtl_ddi_get_config;
> > } else if (IS_DG2(dev_priv)) {
> > encoder->enable_clock = intel_mpllb_enable;
> > --
> > 2.34.1
> >
next prev parent reply other threads:[~2023-02-21 13:23 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-05 12:54 [Intel-gfx] [PATCH v2 00/21] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 01/21] drm/i915/mtl: Initial DDI port setup Mika Kahola
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 02/21] drm/i915/mtl: Add DP rates Mika Kahola
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 03/21] drm/i915/mtl: Create separate reg file for PICA registers Mika Kahola
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 04/21] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming Mika Kahola
2023-01-05 14:18 ` Jani Nikula
2023-01-09 9:49 ` Jani Nikula
2023-01-09 10:31 ` Kahola, Mika
2023-02-07 16:49 ` Gustavo Sousa
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 05/21] drm/i915/mtl: Add C10 phy programming for HDMI Mika Kahola
2023-01-05 15:35 ` kernel test robot
2023-01-05 16:06 ` kernel test robot
2023-01-05 16:16 ` kernel test robot
2023-01-05 16:47 ` kernel test robot
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 06/21] drm/i915/mtl: Add vswing programming for C10 phys Mika Kahola
2023-02-07 16:52 ` Gustavo Sousa
2023-02-07 17:35 ` Gustavo Sousa
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 07/21] drm/i915/mtl: Add support for PM DEMAND Mika Kahola
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 08/21] drm/i915/mtl: C20 PLL programming Mika Kahola
2023-02-07 16:53 ` Gustavo Sousa
2023-02-21 13:18 ` Kahola, Mika
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 09/21] drm/i915/mtl: C20 HW readout Mika Kahola
2023-02-07 16:54 ` Gustavo Sousa
2023-02-23 9:47 ` Kahola, Mika
2023-02-23 10:36 ` Kahola, Mika
2023-03-24 20:51 ` Gustavo Sousa
2023-03-27 9:07 ` Imre Deak
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 10/21] drm/i915/mtl: C20 port clock calculation Mika Kahola
2023-01-05 16:47 ` kernel test robot
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 11/21] drm/i915/mtl: C20 HDMI state calculations Mika Kahola
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 12/21] drm/i915/mtl: Add voltage swing sequence for C20 Mika Kahola
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 13/21] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA Mika Kahola
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 14/21] drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll Mika Kahola
2023-02-07 16:55 ` Gustavo Sousa
2023-02-21 13:23 ` Kahola, Mika [this message]
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 15/21] drm/i915/mtl: Readout Thunderbolt HW state Mika Kahola
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 16/21] drm/i915/mtl: Enable TC ports Mika Kahola
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 17/21] drm/i915/mtl: MTL PICA hotplug detection Mika Kahola
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 18/21] drm/i915/mtl: Define mask for DDI AUX interrupts Mika Kahola
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 19/21] drm/i915/mtl: Power up TCSS Mika Kahola
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 20/21] drm/i915/mtl: TypeC HPD live status query Mika Kahola
2023-01-05 12:54 ` [Intel-gfx] [PATCH v2 21/21] drm/i915/mtl: Pin assignment for TypeC Mika Kahola
2023-01-26 14:40 ` Luca Coelho
2023-01-26 14:43 ` Luca Coelho
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