RE: [PATCH 0/5] clk: renesas: Add MFIS clock

From: Biju Das <biju.das.jz@bp.renesas.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Julien Massot <julien.massot@iot.bzh>,
	"linux-renesas-soc@vger.kernel.org" 
	<linux-renesas-soc@vger.kernel.org>
Subject: RE: [PATCH 0/5] clk: renesas: Add MFIS clock
Date: Fri, 11 Dec 2020 15:49:11 +0000	[thread overview]
Message-ID: <TYBPR01MB5309B90B607BC18FBCEBE42586CA0@TYBPR01MB5309.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <CAMuHMdUZOv=Or5JJZmAVwn2fjA=fP_texF9ZttKaHVY-YLjRCg@mail.gmail.com>

Hi Geert,

> Subject: Re: [PATCH 0/5] clk: renesas: Add MFIS clock
> 
> Hi Biju,
> 
> On Thu, Dec 10, 2020 at 4:47 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > > Subject: Re: [PATCH 0/5] clk: renesas: Add MFIS clock On 12/10/20
> > > 3:57 PM, Biju Das wrote:
> > > >> Subject: [PATCH 0/5] clk: renesas: Add MFIS clock
> > > >>
> > > >> This series adds the missing MFIS clocks for most Reneas R-Car
> > > >> Gen3
> > > SoCs.
> > > >> I have tested this series on E3, M3, and H3 based boards, I don't
> > > >> have access to D3 nor V3 boards.
> > > >
> > > > Just a question, Can you explain what test have you done with MFIS
> > > module?
> > > A basic usage I did is to store and read a byte into one of the
> > > communication register MFISARIICR / MFISAREMBR, a more complex usage
> > > is to trigger interrupts between Linux and the realtime processor,
> > > using a mailbox driver, that I didn't post yet.
> >
> > Thanks for the explanation.
> >
> > FYI, As per R-Car Gen3 HW manual RCar-D3 doesn't have RT Core.
> 
> But R-Car D3 still has (a subset of) the MFIS.

Yes, True. But currently I don't know it's usage on D3.

Thanks and regards,
Biju