From: Andrew Lunn <andrew@lunn.ch>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: hauke@hauke-m.de, netdev@vger.kernel.org,
vivien.didelot@gmail.com, f.fainelli@gmail.com,
olteanv@gmail.com, davem@davemloft.net, kuba@kernel.org,
linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH 1/2] net: dsa: lantiq_gswip: Enable GSWIP_MII_CFG_EN also for internal PHYs
Date: Sun, 3 Jan 2021 03:09:14 +0100 [thread overview]
Message-ID: <X/EnSv8gyprpOWRr@lunn.ch> (raw)
In-Reply-To: <20210103012544.3259029-2-martin.blumenstingl@googlemail.com>
On Sun, Jan 03, 2021 at 02:25:43AM +0100, Martin Blumenstingl wrote:
> Enable GSWIP_MII_CFG_EN also for internal PHYs to make traffic flow.
> Without this the PHY link is detected properly and ethtool statistics
> for TX are increasing but there's no RX traffic coming in.
>
> Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
> Cc: stable@vger.kernel.org
Hi Martin
No need to Cc: stable. David or Jakub will handle the backport to
stable. You should however set the subject to [PATCH net 1/2] and
base the patches on the net tree, not net-next.
Andrew
next prev parent reply other threads:[~2021-01-03 2:10 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-03 1:25 [PATCH 0/2] net: dsa: lantiq_gswip: two fixes for -net/-stable Martin Blumenstingl
2021-01-03 1:25 ` [PATCH 1/2] net: dsa: lantiq_gswip: Enable GSWIP_MII_CFG_EN also for internal PHYs Martin Blumenstingl
2021-01-03 1:35 ` Hauke Mehrtens
2021-01-03 2:09 ` Andrew Lunn [this message]
2021-01-03 2:12 ` Martin Blumenstingl
2021-01-04 21:52 ` Jakub Kicinski
2021-01-04 23:54 ` Martin Blumenstingl
2021-01-04 19:53 ` Florian Fainelli
2021-01-03 1:25 ` [PATCH 2/2] net: dsa: lantiq_gswip: Fix GSWIP_MII_CFG(p) register access Martin Blumenstingl
2021-01-03 1:36 ` Hauke Mehrtens
2021-01-04 19:58 ` Florian Fainelli
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