Re: [Intel-gfx] [PATCH] drm/i915/dgfx: Temporary hammer to keep autosuspend control 'on'

From: Andi Shyti <andi.shyti@linux.intel.com>
To: Anshuman Gupta <anshuman.gupta@intel.com>
Cc: intel-gfx@lists.freedesktop.org, matthew.auld@intel.com,
	rodrigo.vivi@intel.com
Subject: Re: [Intel-gfx] [PATCH] drm/i915/dgfx: Temporary hammer to keep autosuspend control 'on'
Date: Wed, 12 Oct 2022 11:21:59 +0200	[thread overview]
Message-ID: <Y0aHNzVct7jHFrTz@ashyti-mobl2.lan> (raw)
In-Reply-To: <20221012083402.1069940-1-anshuman.gupta@intel.com>

Hi Anshuman,

On Wed, Oct 12, 2022 at 02:04:02PM +0530, Anshuman Gupta wrote:
> DGFX platforms has lmem and cpu can access the lmem objects
> via mmap and i915 internal i915_gem_object_pin_map() for
> i915 own usages. Both of these methods has pre-requisite
> requirement to keep GFX PCI endpoint in D0 for a supported
> iomem transaction over PCI link. (Refer PCIe specs 5.3.1.4.1)
> 
> Both DG1/DG2 have a hardware bug that violates the PCIe specs
> and support the iomem read write transaction over PCIe bus despite
> endpoint is D3 state.
> Due to above H/W bug, we had never observed any issue with i915 runtime
> PM versus lmem access.
> But this issue becomes visible when PCIe gfx endpoint's upstream
> bridge enters to D3, at this point any lmem read/write access will be
> returned as unsupported request. But again this issue is not observed
> on every platform because it has been observed on few host machines
> DG1/DG2 endpoint's upstream bridge does not bind with pcieport driver.
> which really disables the PCIe  power savings and leaves the bridge
> at D0 state.
> 
> Till we fix all issues related to runtime PM, we need
> to keep autosupend control to 'on' on all discrete platforms with lmem.

if it's only DG1 and DG2... why do we need to do it for every
platform?

Besides... is this a hack, workaround, permanent solution?

Andi