From: Borislav Petkov <bp@alien8.de>
To: Justin He <Justin.He@arm.com>
Cc: Len Brown <lenb@kernel.org>, James Morse <James.Morse@arm.com>,
Tony Luck <tony.luck@intel.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Robert Richter <rric@kernel.org>,
Robert Moore <robert.moore@intel.com>,
Qiuxu Zhuo <qiuxu.zhuo@intel.com>,
Yazen Ghannam <yazen.ghannam@amd.com>,
Jan Luebbe <jlu@pengutronix.de>,
Khuong Dinh <khuong@os.amperecomputing.com>,
Kani Toshi <toshi.kani@hpe.com>, Ard Biesheuvel <ardb@kernel.org>,
"linux-acpi@vger.kernel.org" <linux-acpi@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
"devel@acpica.org" <devel@acpica.org>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Shuai Xue <xueshuai@linux.alibaba.com>,
Jarkko Sakkinen <jarkko@kernel.org>,
"linux-efi@vger.kernel.org" <linux-efi@vger.kernel.org>,
nd <nd@arm.com>, kernel test robot <lkp@intel.com>
Subject: Re: [PATCH v8 6/7] apei/ghes: Use unrcu_pointer for cmpxchg
Date: Thu, 13 Oct 2022 15:37:42 +0200 [thread overview]
Message-ID: <Y0gUpoaUBKw/jjaD@zn.tnic> (raw)
In-Reply-To: <DBBPR08MB4538D5A85F707632ACCB70A4F7229@DBBPR08MB4538.eurprd08.prod.outlook.com>
On Wed, Oct 12, 2022 at 12:04:57PM +0000, Justin He wrote:
> I have a concern about what if cmpxchg failed? Do we have to still
> guarantee the ordering since cmpxchg will not imply a smp_mb if it
> failed.
Of course it will imply that. At least on x86 it does. smp_wmb() is a
compiler barrier there and cmpxchg() already has that barrier semantics
by clobbering "memory". I'm pretty sure you should have the same thing
on ARM.
And even if that weren't the case, the write barrier is, as the comment
says, "new_cache must be put into array after its contents are written".
Are we writing anything into the cache if cmpxchg fails?
> Besides, I didn't find the paired smp_mb or smp_rmb for this smp_wmb.
Why would there be pairs? I don't understand that statement here.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2022-10-13 13:37 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-10 2:35 [PATCH v8 0/7] Make ghes_edac a proper module Jia He
2022-10-10 2:35 ` [PATCH v8 1/7] efi/cper: export several helpers for ghes_edac to use Jia He
2022-10-10 2:35 ` [PATCH v8 2/7] EDAC/ghes: Add a notifier for reporting memory errors Jia He
2022-10-10 2:35 ` [PATCH v8 3/7] EDAC/ghes: Prepare to make ghes_edac a proper module Jia He
2022-10-10 2:35 ` [PATCH v8 4/7] EDAC/ghes: Make ghes_edac a proper module to remove the dependency on ghes Jia He
2022-10-10 2:35 ` [PATCH v8 5/7] EDAC: Add the ghes_get_devices() check for chipset-specific edac drivers Jia He
2022-10-10 2:35 ` [PATCH v8 6/7] apei/ghes: Use unrcu_pointer for cmpxchg Jia He
2022-10-11 10:33 ` Borislav Petkov
2022-10-11 14:32 ` Justin He
2022-10-11 14:45 ` Borislav Petkov
2022-10-12 4:35 ` Justin He
2022-10-12 12:04 ` Justin He
2022-10-13 13:37 ` Borislav Petkov [this message]
2022-10-13 15:41 ` Ard Biesheuvel
2022-10-13 16:37 ` Borislav Petkov
2022-10-13 16:45 ` Peter Zijlstra
2022-10-13 17:42 ` Borislav Petkov
2022-10-14 9:40 ` Ard Biesheuvel
2022-10-14 19:40 ` Borislav Petkov
2022-10-14 12:00 ` Justin He
2022-10-14 14:31 ` Ard Biesheuvel
2022-10-14 15:10 ` Peter Zijlstra
2022-10-14 15:24 ` Ard Biesheuvel
2022-10-17 8:47 ` Justin He
2022-10-17 9:27 ` Ard Biesheuvel
2022-10-17 11:57 ` Justin He
2022-10-13 16:41 ` Peter Zijlstra
2022-10-10 2:35 ` [PATCH v8 7/7] EDAC/igen6: Return consistent errno when another edac driver is enabled Jia He
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