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From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: matthew.gerlach@linux.intel.com
Cc: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com,
	basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
	mdf@kernel.org, linux-fpga@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	tianfei.zhang@intel.com, corbet@lwn.net,
	gregkh@linuxfoundation.org, linux-serial@vger.kernel.org,
	jirislaby@kernel.org, geert+renesas@glider.be,
	niklas.soderlund+renesas@ragnatech.se, macro@orcam.me.uk,
	johan@kernel.org, lukas@wunner.de, ilpo.jarvinen@linux.intel.com,
	marpagan@redhat.com, bagasdotme@gmail.com
Subject: Re: [PATCH v7 4/4] tty: serial: 8250: add DFL bus driver for Altera 16550.
Date: Tue, 20 Dec 2022 19:09:20 +0200	[thread overview]
Message-ID: <Y6HsQJQMDnHgTesF@smile.fi.intel.com> (raw)
In-Reply-To: <20221220163652.499831-5-matthew.gerlach@linux.intel.com>

On Tue, Dec 20, 2022 at 08:36:52AM -0800, matthew.gerlach@linux.intel.com wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> 
> Add a Device Feature List (DFL) bus driver for the Altera
> 16550 implementation of UART.

In general the code here looks good to me, but one thing to discuss due to
comment to the previous patch(es).

...

> +	u64 *p;
> +
> +	p = dfh_find_param(dfl_dev, DFHv1_PARAM_ID_CLK_FRQ);
> +	if (!p)
> +		return dev_err_probe(dev, -EINVAL, "missing CLK_FRQ param\n");
> +
> +	p++;
> +	uart->port.uartclk = *p;

So, here and the below is using always the second u64 from the returned data.
Does it mean:
- we always skip the first u64 from the returned buffer and hence... (see below)
- we may actually return the second u64 as a plain number (not a pointer) from
  (an additional?) API? In such case we would not need to take care about this
  p++; lines here and there.
- we have fixed length of the data, returned by find_param(), i.e. 2 u64 words?

-- 
With Best Regards,
Andy Shevchenko



  reply	other threads:[~2022-12-20 17:15 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-20 16:36 [PATCH v7 0/4] Enhance definition of DFH and use enhancements for UART driver matthew.gerlach
2022-12-20 16:36 ` [PATCH v7 1/4] Documentation: fpga: dfl: Add documentation for DFHv1 matthew.gerlach
2022-12-20 16:53   ` Andy Shevchenko
2022-12-21 16:52     ` matthew.gerlach
2022-12-20 16:36 ` [PATCH v7 2/4] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2022-12-20 16:54   ` Andy Shevchenko
2022-12-20 16:36 ` [PATCH v7 3/4] fpga: dfl: add basic support for DFHv1 matthew.gerlach
2022-12-20 17:03   ` Andy Shevchenko
2022-12-21 19:14     ` matthew.gerlach
2022-12-26  3:15       ` Xu Yilun
2022-12-31 20:46         ` matthew.gerlach
2023-01-03  4:22           ` Xu Yilun
2023-01-03 19:50             ` matthew.gerlach
2023-01-04  2:34               ` Xu Yilun
2022-12-21 11:58   ` Ilpo Järvinen
2022-12-21 22:29     ` matthew.gerlach
2022-12-20 16:36 ` [PATCH v7 4/4] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2022-12-20 17:09   ` Andy Shevchenko [this message]
2022-12-21 17:26     ` Marco Pagani
2022-12-21 19:52       ` Marco Pagani
2022-12-21 22:37         ` matthew.gerlach
2022-12-21 22:16     ` matthew.gerlach

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