All of lore.kernel.org
 help / color / mirror / Atom feed
From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Eric Biggers <ebiggers@kernel.org>,
	"linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>,
	linux-arm-msm <linux-arm-msm@vger.kernel.org>,
	Satya Tangirala <satyat@google.com>,
	Andy Gross <agross@kernel.org>
Subject: Re: [PATCH v5 6/9] firmware: qcom_scm: update comment for ICE-related functions
Date: Thu, 21 Jan 2021 09:30:05 -0600	[thread overview]
Message-ID: <YAmd/b2y7vvp7udE@builder.lan> (raw)
In-Reply-To: <CAPDyKFoOL2Dsqb=nKw5hF5hiVLn-TDHWH4Th9icvoLY4aJtpSA@mail.gmail.com>

On Thu 21 Jan 08:42 CST 2021, Ulf Hansson wrote:

> - trimmed cc-list
> 
> On Thu, 21 Jan 2021 at 10:03, Eric Biggers <ebiggers@kernel.org> wrote:
> >
> > From: Eric Biggers <ebiggers@google.com>
> >
> > The SCM calls QCOM_SCM_ES_INVALIDATE_ICE_KEY and
> > QCOM_SCM_ES_CONFIG_SET_ICE_KEY are also needed for eMMC inline
> > encryption support, not just for UFS.  Update the comments accordingly.
> >
> > Reviewed-by: Satya Tangirala <satyat@google.com>
> > Signed-off-by: Eric Biggers <ebiggers@google.com>
> 
> Björn, may I have your ack on this one? I intend to queue this via my mmc tree.
> 

Certainly, sorry for not paying attention.

Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>


And I presume I'll take the dts patch (8/9) through the Qcom tree...

Regards,
Bjorn

> Kind regards
> Uffe
> 
> > ---
> >  drivers/firmware/qcom_scm.c | 16 +++++++++++-----
> >  1 file changed, 11 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
> > index 7be48c1bec96d..f57779fc7ee93 100644
> > --- a/drivers/firmware/qcom_scm.c
> > +++ b/drivers/firmware/qcom_scm.c
> > @@ -965,8 +965,11 @@ EXPORT_SYMBOL(qcom_scm_ice_available);
> >   * qcom_scm_ice_invalidate_key() - Invalidate an inline encryption key
> >   * @index: the keyslot to invalidate
> >   *
> > - * The UFSHCI standard defines a standard way to do this, but it doesn't work on
> > - * these SoCs; only this SCM call does.
> > + * The UFSHCI and eMMC standards define a standard way to do this, but it
> > + * doesn't work on these SoCs; only this SCM call does.
> > + *
> > + * It is assumed that the SoC has only one ICE instance being used, as this SCM
> > + * call doesn't specify which ICE instance the keyslot belongs to.
> >   *
> >   * Return: 0 on success; -errno on failure.
> >   */
> > @@ -995,10 +998,13 @@ EXPORT_SYMBOL(qcom_scm_ice_invalidate_key);
> >   *                 units, e.g. 1 = 512 bytes, 8 = 4096 bytes, etc.
> >   *
> >   * Program a key into a keyslot of Qualcomm ICE (Inline Crypto Engine), where it
> > - * can then be used to encrypt/decrypt UFS I/O requests inline.
> > + * can then be used to encrypt/decrypt UFS or eMMC I/O requests inline.
> > + *
> > + * The UFSHCI and eMMC standards define a standard way to do this, but it
> > + * doesn't work on these SoCs; only this SCM call does.
> >   *
> > - * The UFSHCI standard defines a standard way to do this, but it doesn't work on
> > - * these SoCs; only this SCM call does.
> > + * It is assumed that the SoC has only one ICE instance being used, as this SCM
> > + * call doesn't specify which ICE instance the keyslot belongs to.
> >   *
> >   * Return: 0 on success; -errno on failure.
> >   */
> > --
> > 2.30.0
> >

  reply	other threads:[~2021-01-21 15:31 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-21  9:01 [PATCH v5 0/9] eMMC inline encryption support Eric Biggers
2021-01-21  9:01 ` [PATCH v5 1/9] mmc: add basic support for inline encryption Eric Biggers
2021-01-21  9:01 ` [PATCH v5 2/9] mmc: cqhci: rename cqhci.c to cqhci-core.c Eric Biggers
2021-01-21  9:01 ` [PATCH v5 3/9] mmc: cqhci: initialize upper 64 bits of 128-bit task descriptors Eric Biggers
2021-01-21  9:01 ` [PATCH v5 4/9] mmc: cqhci: add support for inline encryption Eric Biggers
2021-01-21 12:44   ` kernel test robot
2021-01-21 13:04   ` Ulf Hansson
2021-01-21 18:17     ` Eric Biggers
2021-01-22  9:21       ` Ulf Hansson
2021-01-21  9:01 ` [PATCH v5 5/9] mmc: cqhci: add cqhci_host_ops::program_key Eric Biggers
2021-01-21  9:01 ` [PATCH v5 6/9] firmware: qcom_scm: update comment for ICE-related functions Eric Biggers
2021-01-21 14:42   ` Ulf Hansson
2021-01-21 15:30     ` Bjorn Andersson [this message]
2021-01-21 16:25       ` Ulf Hansson
2021-01-21  9:01 ` [PATCH v5 7/9] dt-bindings: mmc: sdhci-msm: add ICE registers and clock Eric Biggers
2021-01-21  9:01 ` [PATCH v5 8/9] arm64: dts: qcom: sdm630: add ICE registers and clocks Eric Biggers
2021-01-21  9:01 ` [PATCH v5 9/9] mmc: sdhci-msm: add Inline Crypto Engine support Eric Biggers

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=YAmd/b2y7vvp7udE@builder.lan \
    --to=bjorn.andersson@linaro.org \
    --cc=agross@kernel.org \
    --cc=ebiggers@kernel.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-mmc@vger.kernel.org \
    --cc=satyat@google.com \
    --cc=ulf.hansson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.