From: Sean Christopherson <seanjc@google.com>
To: Like Xu <like.xu@linux.intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/4] KVM: vmx/pmu: Add MSR_ARCH_LBR_DEPTH emulation for Arch LBR
Date: Mon, 1 Mar 2021 14:34:00 -0800 [thread overview]
Message-ID: <YD1r2G1UQjVXkUk5@google.com> (raw)
In-Reply-To: <20210203135714.318356-2-like.xu@linux.intel.com>
On Wed, Feb 03, 2021, Like Xu wrote:
> @@ -348,10 +352,26 @@ static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu,
> return true;
> }
>
> +/*
> + * Check if the requested depth values is supported
> + * based on the bits [0:7] of the guest cpuid.1c.eax.
> + */
> +static bool arch_lbr_depth_is_valid(struct kvm_vcpu *vcpu, u64 depth)
> +{
> + struct kvm_cpuid_entry2 *best;
> +
> + best = kvm_find_cpuid_entry(vcpu, 0x1c, 0);
> + if (depth && best)
> + return (best->eax & 0xff) & (1ULL << (depth / 8 - 1));
I believe this will genereate undefined behavior if depth > 64. Or if depth < 8.
And I believe this check also needs to enforce that depth is a multiple of 8.
For each bit n set in this field, the IA32_LBR_DEPTH.DEPTH value 8*(n+1) is
supported.
Thus it's impossible for 0-7, 9-15, etc... to be legal depths.
> +
> + return false;
> +}
> +
next prev parent reply other threads:[~2021-03-02 7:12 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-03 13:57 [PATCH v2 0/4] KVM: x86/pmu: Guest Architectural LBR Enabling Like Xu
2021-02-03 13:57 ` [PATCH v2 1/4] KVM: vmx/pmu: Add MSR_ARCH_LBR_DEPTH emulation for Arch LBR Like Xu
2021-03-01 22:34 ` Sean Christopherson [this message]
2021-03-02 2:52 ` Like Xu
2021-02-03 13:57 ` [PATCH v2 2/4] KVM: vmx/pmu: Add MSR_ARCH_LBR_CTL " Like Xu
2021-02-03 13:57 ` [PATCH v2 3/4] KVM: vmx/pmu: Add Arch LBR emulation and its VMCS field Like Xu
2021-02-03 13:57 ` [PATCH v2 4/4] KVM: x86: Expose Architectural LBR CPUID and its XSAVES bit Like Xu
2021-02-03 14:37 ` Paolo Bonzini
2021-02-04 0:59 ` Xu, Like
2021-02-05 8:16 ` Xu, Like
2021-02-05 11:00 ` Paolo Bonzini
2021-02-07 1:02 ` Xu, Like
2021-02-08 10:31 ` Paolo Bonzini
2021-04-14 1:00 ` Xu, Like
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