Re: [RFC PATCH] memory: renesas-rpc-if: Correct QSPI data transfer in Manual mode

From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	Duc Nguyen <duc.nguyen.ub@renesas.com>,
	Andrew Gabbasov <andrew_gabbasov@mentor.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [RFC PATCH] memory: renesas-rpc-if: Correct QSPI data transfer in Manual mode
Date: Fri, 24 Sep 2021 14:35:32 +0200	[thread overview]
Message-ID: <YU3GFMmCjjG3eS+L@kunai> (raw)
In-Reply-To: <11355367-8d20-5a17-70da-618d87301407@canonical.com>

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Hi Krzysztof,

> > So, in 16-bit transfer (SPIDE[3:0]=b'1100), SMWDR0 should be
> > accessed by 16-bit width.
> > Similar to SMWDR1, SMDDR0/1 registers.
> > In current code, SMWDR0 register is accessed by regmap_write()
> > that only set up to do 32-bit width.
> 
> Is this part something worth splitting to its own patch?

I don't think so because it is related. The patch ensures that a) only
8, 4, 2, or 1 byte blocks are used and b) whatever is used, the access
width to the data registers is proper. Only the combination of both
fixes the data corruption. Also, for backporting, it would be good to
not introduce dependencies, I think.

> You sent the patch just slightly after this one:
> https://lore.kernel.org/lkml/20210922184830.29147-1-andrew_gabbasov@mentor.com/
> 
> Are you solving similar problem?

Unlikely. I do not have HyperFlash on my board, so I can't test. But as
I understand the docs, HyperFlash in deed doubles the granularity from 8
to 16 bits when using memcpy. But I am dealing with MMIO register
accesses in manual mode here.

Thanks for the review,

   Wolfram

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