From: Mark Brown <broonie@kernel.org>
To: Kamal Dasu <kdasu.kdev@gmail.com>
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com,
yendapally.reddy@broadcom.com, Kamal Dasu <kdasu@broadcom.com>
Subject: Re: [PATCH 2/3] spi: bcm-qspi: clear MSPI spifie interrupt during probe
Date: Mon, 11 Oct 2021 13:15:33 +0100 [thread overview]
Message-ID: <YWQq5cOvDTgf5rql@sirena.org.uk> (raw)
In-Reply-To: <20211008203603.40915-3-kdasu.kdev@gmail.com>
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On Fri, Oct 08, 2021 at 04:36:02PM -0400, Kamal Dasu wrote:
> From: Kamal Dasu <kdasu@broadcom.com>
>
> Intermittent Kernel crash has been observed on probe in
> bcm_qspi_mspi_l2_isr() handler when the MSPI spifie interrupt bit
> has not been cleared before registering for interrupts.
> Fix the driver to move SoC specific custom interrupt handling code
> before we register IRQ in probe. Also clear MSPI interrupt status
> resgiter prior to registering IRQ handlers.
Fixes should come at the start of a series before any new code so that
they can be sent as bug fixes without pulling in any of the new work.
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next prev parent reply other threads:[~2021-10-11 12:15 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-08 20:36 [PATCH 0/3] spi-bcm-qspi spcr3 enahancements Kamal Dasu
2021-10-08 20:36 ` [PATCH 1/3] spi: bcm-qspi: Add mspi spcr3 32/64-bits xfer mode Kamal Dasu
2021-10-11 2:54 ` Florian Fainelli
2021-10-08 20:36 ` [PATCH 2/3] spi: bcm-qspi: clear MSPI spifie interrupt during probe Kamal Dasu
2021-10-11 2:53 ` Florian Fainelli
2021-10-11 12:15 ` Mark Brown [this message]
2021-10-08 20:36 ` [PATCH 3/3] spi: bcm-qspi: add support for 3-wire mode for half duplex transfer Kamal Dasu
2021-10-11 2:54 ` Florian Fainelli
2021-10-11 17:01 ` [PATCH 0/3] spi-bcm-qspi spcr3 enahancements Mark Brown
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