From: "Roger Pau Monné" <roger.pau@citrix.com>
To: "Marek Marczykowski-Górecki" <marmarek@invisiblethingslab.com>
Cc: xen-devel@lists.xenproject.org,
Andrew Cooper <andrew.cooper3@citrix.com>,
George Dunlap <george.dunlap@citrix.com>,
Jan Beulich <jbeulich@suse.com>, Julien Grall <julien@xen.org>,
Stefano Stabellini <sstabellini@kernel.org>, Wei Liu <wl@xen.org>
Subject: Re: [PATCH v3 1/2] ns16550: reject IRQ above nr_irqs_gsi
Date: Wed, 11 May 2022 09:57:20 +0200 [thread overview]
Message-ID: <YntsYOMA9fYXzpU5@Air-de-Roger> (raw)
In-Reply-To: <YntjzqQl0CIeGzR4@Air-de-Roger>
On Wed, May 11, 2022 at 09:20:46AM +0200, Roger Pau Monné wrote:
> Subject line needs to be updated :).
>
> On Tue, May 10, 2022 at 05:58:23PM +0200, Marek Marczykowski-Górecki wrote:
> > Intel LPSS has INTERRUPT_LINE set to 0xff by default, that is declared
> > by the PCI Local Bus Specification Revision 3.0 (from 2004) as
> > "unknown"/"no connection". Fallback to poll mode in this case.
Forgot to comment: you should also mention that this 0xff special
handling is for x86 only, other arches can use other meanings for the
INTERRUPT_LINE register.
Likely this also implies that the 0xff check should be protected by
CONFIG_X86 (albeit I think that code is already only reachable from
x86 as Arm doesn't yet enable CONFIG_PCI).
Thanks, Roger.
prev parent reply other threads:[~2022-05-11 7:57 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-10 15:58 [PATCH v3 1/2] ns16550: reject IRQ above nr_irqs_gsi Marek Marczykowski-Górecki
2022-05-10 15:58 ` [PATCH v3 2/2] ns16550: Add more device IDs for Intel LPSS UART Marek Marczykowski-Górecki
2022-05-11 7:20 ` [PATCH v3 1/2] ns16550: reject IRQ above nr_irqs_gsi Roger Pau Monné
2022-05-11 7:57 ` Roger Pau Monné [this message]
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