From: Matt Roper <matthew.d.roper@intel.com>
To: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/dg2: Add workaround 22014600077
Date: Wed, 18 May 2022 08:24:30 -0700 [thread overview]
Message-ID: <YoUPrn9oVsEnPBsx@mdroper-desk1.amr.corp.intel.com> (raw)
In-Reply-To: <20220517212905.24212-1-swathi.dhanavanthri@intel.com>
On Tue, May 17, 2022 at 02:29:05PM -0700, Swathi Dhanavanthri wrote:
> Signed-off-by: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++++++++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 98ede9c93f00..2063c8758934 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1068,6 +1068,7 @@
> #define GEN9_ENABLE_GPGPU_PREEMPTION REG_BIT(2)
>
> #define GEN10_CACHE_MODE_SS _MMIO(0xe420)
> +#define ENABLE_EU_COUNT_FOR_TDL_FLUSH REG_BIT(10)
The whitespace on this line is still wrong. I guess we can fix that up
while applying the patch though.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> #define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
> #define FLOAT_BLEND_OPTIMIZATION_ENABLE REG_BIT(4)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 756807c4b405..73b59ea6fd3b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2178,6 +2178,16 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB);
> }
>
> + if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) ||
> + IS_DG2_G10(i915)) {
> + /* Wa_22014600077:dg2 */
> + wa_add(wal, GEN10_CACHE_MODE_SS, 0,
> + _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH),
> + 0 /* Wa_14012342262 :write-only reg, so skip
> + verification */,
> + true);
> + }
> +
> if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> /*
> --
> 2.20.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
next prev parent reply other threads:[~2022-05-18 15:24 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-17 21:29 [Intel-gfx] [PATCH v2] drm/i915/dg2: Add workaround 22014600077 Swathi Dhanavanthri
2022-05-17 22:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Add workaround 22014600077 (rev2) Patchwork
2022-05-17 22:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-18 4:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-05-18 21:11 ` Dhanavanthri, Swathi
2022-05-18 22:21 ` Vudum, Lakshminarayana
2022-05-18 15:24 ` Matt Roper [this message]
2022-05-18 22:03 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2022-05-19 16:54 ` Matt Roper
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