Re: [PATCH 5.10.y-cip 6/7] serial: 8250_em: Add serial8250_em_{reg_update(),out_helper()}

From: Pavel Machek <pavel@denx.de>
To: Biju Das <biju.das.jz@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>,
	Chris Paterson <chris.paterson2@renesas.com>,
	Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Subject: Re: [PATCH 5.10.y-cip 6/7] serial: 8250_em: Add serial8250_em_{reg_update(),out_helper()}
Date: Wed, 14 Jun 2023 12:18:46 +0200	[thread overview]
Message-ID: <ZImUBg3er1tsqZzz@duo.ucw.cz> (raw)
In-Reply-To: <20230613132339.150671-7-biju.das.jz@bp.renesas.com>

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Hi!

> As per RZ/V2M hardware manual(Rev.1.30 Jun, 2022), UART IP has a
> restriction as mentioned below.
> 
> 40.6.1 Point for Caution when Changing the Register Settings:
> 
> When changing the settings of the following registers, a PRESETn master
> reset or FIFO reset + SW reset (FCR[2],FCR[1], HCR0[7]) must be input to
> re-initialize them.
> 
> Target Registers: FCR, LCR, MCR, DLL, DLM, HCR0.

So how does this work? AFAIU looking at the previous patch, FCR is
write only, you get IIR register when you try to read it.

> +static void serial8250_em_reg_update(struct uart_port *p, int off, int value)
> +{
> +	unsigned int ier, fcr, lcr, mcr, hcr0;
> +
> +	ier = serial8250_em_serial_in(p, UART_IER);
> +	fcr = serial8250_em_serial_in(p, UART_FCR_EM);

So here you read IIR...

> +	serial8250_em_serial_out_helper(p, UART_FCR_EM, fcr);

...and write it back to fcr?

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,        Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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