From: Frank Li <Frank.li@nxp.com>
To: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
fancer.lancer@gmail.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH v20 02/19] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
Date: Mon, 29 Jan 2024 17:42:20 -0500 [thread overview]
Message-ID: <ZbgpzPjS7Jhe8fq5@lizhi-Precision-Tower-5810> (raw)
In-Reply-To: <20230825093219.2685912-3-yoshihiro.shimoda.uh@renesas.com>
On Fri, Aug 25, 2023 at 06:32:02PM +0900, Yoshihiro Shimoda wrote:
> This is a preparation before adding the Msg-type outbound iATU
> mapping. The respective update will require two more arguments added
> to __dw_pcie_prog_outbound_atu(). That will make the already
> complicated function prototype even more hard to comprehend accepting
> _eight_ arguments. In order to prevent that and keep the code
> more-or-less readable all the outbound iATU-related arguments are
> moved to the new config-structure: struct dw_pcie_ob_atu_cfg pointer
> to which shall be passed to dw_pcie_prog_outbound_atu(). The structure
> is supposed to be locally defined and populated with the outbound iATU
> settings implied by the caller context.
>
> As a result of the denoted change there is no longer need in having
> the two distinctive methods for the Host and End-point outbound iATU
> setups since the corresponding code can directly call the
> dw_pcie_prog_outbound_atu() method with the config-structure
> populated. Thus dw_pcie_prog_ep_outbound_atu() is dropped.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Yoshihiro:
I want to use this patch to send out PME message when suspend,
which should be similar with raise INTx. Can I include your this patches in
my PME enable patches list if your patch still not merge yet.
Frank
> ---
> .../pci/controller/dwc/pcie-designware-ep.c | 21 +++++---
> .../pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++------
> drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++-----------
> drivers/pci/controller/dwc/pcie-designware.h | 15 ++++--
> 4 files changed, 77 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index ab87ea3b0986..747d5bc07222 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -182,9 +182,8 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type,
> return 0;
> }
>
> -static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
> - phys_addr_t phys_addr,
> - u64 pci_addr, size_t size)
> +static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep,
> + struct dw_pcie_ob_atu_cfg *atu)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> u32 free_win;
> @@ -196,13 +195,13 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
> return -EINVAL;
> }
>
> - ret = dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win, PCIE_ATU_TYPE_MEM,
> - phys_addr, pci_addr, size);
> + atu->index = free_win;
> + ret = dw_pcie_prog_outbound_atu(pci, atu);
> if (ret)
> return ret;
>
> set_bit(free_win, ep->ob_window_map);
> - ep->outbound_addr[free_win] = phys_addr;
> + ep->outbound_addr[free_win] = atu->cpu_addr;
>
> return 0;
> }
> @@ -305,8 +304,14 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> int ret;
> struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> -
> - ret = dw_pcie_ep_outbound_atu(ep, func_no, addr, pci_addr, size);
> + struct dw_pcie_ob_atu_cfg atu = { 0 };
> +
> + atu.func_no = func_no;
> + atu.type = PCIE_ATU_TYPE_MEM;
> + atu.cpu_addr = addr;
> + atu.pci_addr = pci_addr;
> + atu.size = size;
> + ret = dw_pcie_ep_outbound_atu(ep, &atu);
> if (ret) {
> dev_err(pci->dev, "Failed to enable address\n");
> return ret;
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 5c8cbc3afae4..01eff83c1f6d 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -551,6 +551,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
> {
> struct dw_pcie_rp *pp = bus->sysdata;
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct dw_pcie_ob_atu_cfg atu = { 0 };
> int type, ret;
> u32 busdev;
>
> @@ -573,8 +574,12 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
> else
> type = PCIE_ATU_TYPE_CFG1;
>
> - ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev,
> - pp->cfg0_size);
> + atu.type = type;
> + atu.cpu_addr = pp->cfg0_base;
> + atu.pci_addr = busdev;
> + atu.size = pp->cfg0_size;
> +
> + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> if (ret)
> return NULL;
>
> @@ -586,6 +591,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
> {
> struct dw_pcie_rp *pp = bus->sysdata;
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct dw_pcie_ob_atu_cfg atu = { 0 };
> int ret;
>
> ret = pci_generic_config_read(bus, devfn, where, size, val);
> @@ -593,9 +599,12 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
> return ret;
>
> if (pp->cfg0_io_shared) {
> - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
> - pp->io_base, pp->io_bus_addr,
> - pp->io_size);
> + atu.type = PCIE_ATU_TYPE_IO;
> + atu.cpu_addr = pp->io_base;
> + atu.pci_addr = pp->io_bus_addr;
> + atu.size = pp->io_size;
> +
> + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> if (ret)
> return PCIBIOS_SET_FAILED;
> }
> @@ -608,6 +617,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
> {
> struct dw_pcie_rp *pp = bus->sysdata;
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct dw_pcie_ob_atu_cfg atu = { 0 };
> int ret;
>
> ret = pci_generic_config_write(bus, devfn, where, size, val);
> @@ -615,9 +625,12 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
> return ret;
>
> if (pp->cfg0_io_shared) {
> - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
> - pp->io_base, pp->io_bus_addr,
> - pp->io_size);
> + atu.type = PCIE_ATU_TYPE_IO;
> + atu.cpu_addr = pp->io_base;
> + atu.pci_addr = pp->io_bus_addr;
> + atu.size = pp->io_size;
> +
> + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> if (ret)
> return PCIBIOS_SET_FAILED;
> }
> @@ -652,6 +665,7 @@ static struct pci_ops dw_pcie_ops = {
> static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> {
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct dw_pcie_ob_atu_cfg atu = { 0 };
> struct resource_entry *entry;
> int i, ret;
>
> @@ -679,10 +693,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> if (pci->num_ob_windows <= ++i)
> break;
>
> - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM,
> - entry->res->start,
> - entry->res->start - entry->offset,
> - resource_size(entry->res));
> + atu.index = i;
> + atu.type = PCIE_ATU_TYPE_MEM;
> + atu.cpu_addr = entry->res->start;
> + atu.pci_addr = entry->res->start - entry->offset;
> + atu.size = resource_size(entry->res);
> +
> + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> if (ret) {
> dev_err(pci->dev, "Failed to set MEM range %pr\n",
> entry->res);
> @@ -692,10 +709,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>
> if (pp->io_size) {
> if (pci->num_ob_windows > ++i) {
> - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO,
> - pp->io_base,
> - pp->io_bus_addr,
> - pp->io_size);
> + atu.index = i;
> + atu.type = PCIE_ATU_TYPE_IO;
> + atu.cpu_addr = pp->io_base;
> + atu.pci_addr = pp->io_bus_addr;
> + atu.size = pp->io_size;
> +
> + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> if (ret) {
> dev_err(pci->dev, "Failed to set IO range %pr\n",
> entry->res);
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 2459f2a61b9b..49b785509576 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -464,56 +464,56 @@ static inline u32 dw_pcie_enable_ecrc(u32 val)
> return val | PCIE_ATU_TD;
> }
>
> -static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
> - int index, int type, u64 cpu_addr,
> - u64 pci_addr, u64 size)
> +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> + const struct dw_pcie_ob_atu_cfg *atu)
> {
> + u64 cpu_addr = atu->cpu_addr;
> u32 retries, val;
> u64 limit_addr;
>
> if (pci->ops && pci->ops->cpu_addr_fixup)
> cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
>
> - limit_addr = cpu_addr + size - 1;
> + limit_addr = cpu_addr + atu->size - 1;
>
> if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) ||
> !IS_ALIGNED(cpu_addr, pci->region_align) ||
> - !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
> + !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) {
> return -EINVAL;
> }
>
> - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_BASE,
> + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE,
> lower_32_bits(cpu_addr));
> - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_BASE,
> + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE,
> upper_32_bits(cpu_addr));
>
> - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LIMIT,
> + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT,
> lower_32_bits(limit_addr));
> if (dw_pcie_ver_is_ge(pci, 460A))
> - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_LIMIT,
> + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT,
> upper_32_bits(limit_addr));
>
> - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_TARGET,
> - lower_32_bits(pci_addr));
> - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_TARGET,
> - upper_32_bits(pci_addr));
> + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET,
> + lower_32_bits(atu->pci_addr));
> + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
> + upper_32_bits(atu->pci_addr));
>
> - val = type | PCIE_ATU_FUNC_NUM(func_no);
> + val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
> if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
> dw_pcie_ver_is_ge(pci, 460A))
> val |= PCIE_ATU_INCREASE_REGION_SIZE;
> if (dw_pcie_ver_is(pci, 490A))
> val = dw_pcie_enable_ecrc(val);
> - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL1, val);
> + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
>
> - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
>
> /*
> * Make sure ATU enable takes effect before any subsequent config
> * and I/O accesses.
> */
> for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
> - val = dw_pcie_readl_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2);
> + val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2);
> if (val & PCIE_ATU_ENABLE)
> return 0;
>
> @@ -525,21 +525,6 @@ static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
> return -ETIMEDOUT;
> }
>
> -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> - u64 cpu_addr, u64 pci_addr, u64 size)
> -{
> - return __dw_pcie_prog_outbound_atu(pci, 0, index, type,
> - cpu_addr, pci_addr, size);
> -}
> -
> -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> - int type, u64 cpu_addr, u64 pci_addr,
> - u64 size)
> -{
> - return __dw_pcie_prog_outbound_atu(pci, func_no, index, type,
> - cpu_addr, pci_addr, size);
> -}
> -
> static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg)
> {
> return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg);
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 755bcb406769..296c5b1ddc91 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -298,6 +298,15 @@ enum dw_pcie_ltssm {
> DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF,
> };
>
> +struct dw_pcie_ob_atu_cfg {
> + int index;
> + int type;
> + u8 func_no;
> + u64 cpu_addr;
> + u64 pci_addr;
> + u64 size;
> +};
> +
> struct dw_pcie_host_ops {
> int (*host_init)(struct dw_pcie_rp *pp);
> void (*host_deinit)(struct dw_pcie_rp *pp);
> @@ -429,10 +438,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
> int dw_pcie_link_up(struct dw_pcie *pci);
> void dw_pcie_upconfig_setup(struct dw_pcie *pci);
> int dw_pcie_wait_for_link(struct dw_pcie *pci);
> -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> - u64 cpu_addr, u64 pci_addr, u64 size);
> -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> - int type, u64 cpu_addr, u64 pci_addr, u64 size);
> +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> + const struct dw_pcie_ob_atu_cfg *atu);
> int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
> u64 cpu_addr, u64 pci_addr, u64 size);
> int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> --
> 2.25.1
>
next prev parent reply other threads:[~2024-01-29 22:42 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-25 9:32 [PATCH v20 00/19] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2023-08-25 9:32 ` [PATCH v20 01/19] PCI: Add INTx Mechanism Messages macros Yoshihiro Shimoda
2023-08-25 9:32 ` [PATCH v20 02/19] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu() Yoshihiro Shimoda
2024-01-29 22:42 ` Frank Li [this message]
2024-01-30 0:46 ` Yoshihiro Shimoda
2023-08-25 9:32 ` [PATCH v20 03/19] PCI: dwc: Add outbound MSG TLPs support Yoshihiro Shimoda
2023-08-25 9:32 ` [PATCH v20 04/19] PCI: designware-ep: Add INTx IRQs support Yoshihiro Shimoda
2023-09-13 23:31 ` Bjorn Helgaas
2023-09-14 7:56 ` Yoshihiro Shimoda
2023-09-15 21:23 ` Bjorn Helgaas
2023-09-19 7:22 ` Yoshihiro Shimoda
2023-09-19 10:39 ` Bjorn Helgaas
2023-09-19 11:55 ` Yoshihiro Shimoda
2023-08-25 9:32 ` [PATCH v20 05/19] PCI: dwc: endpoint: Add multiple PFs support for dbi2 Yoshihiro Shimoda
2023-08-25 9:32 ` [PATCH v20 06/19] PCI: dwc: Add dw_pcie_link_set_max_link_width() Yoshihiro Shimoda
2023-08-25 9:32 ` [PATCH v20 07/19] PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling Yoshihiro Shimoda
2023-09-14 16:00 ` Bjorn Helgaas
2023-09-14 20:48 ` Serge Semin
2023-09-14 20:59 ` Bjorn Helgaas
2023-09-14 21:25 ` Serge Semin
2023-08-25 9:32 ` [PATCH v20 08/19] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting Yoshihiro Shimoda
2023-08-25 9:32 ` [PATCH v20 09/19] PCI: dwc: Add EDMA_UNROLL capability flag Yoshihiro Shimoda
2023-09-14 16:09 ` Bjorn Helgaas
2023-09-14 21:07 ` Serge Semin
2023-08-25 9:32 ` [PATCH v20 10/19] PCI: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
2023-08-25 9:32 ` [PATCH v20 11/19] PCI: dwc: Expose dw_pcie_write_dbi2() " Yoshihiro Shimoda
2023-08-25 18:18 ` Serge Semin
2023-08-25 9:32 ` [PATCH v20 12/19] PCI: dwc: endpoint: Introduce .pre_init() and .deinit() Yoshihiro Shimoda
2023-08-25 9:32 ` [PATCH v20 13/19] dt-bindings: PCI: dwc: Update maxItems of reg and reg-names Yoshihiro Shimoda
2023-08-25 9:32 ` [PATCH v20 14/19] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
2023-08-31 13:12 ` Geert Uytterhoeven
2023-09-01 1:13 ` Yoshihiro Shimoda
2023-08-25 9:32 ` [PATCH v20 15/19] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
2023-08-31 13:16 ` Geert Uytterhoeven
2023-09-01 1:13 ` Yoshihiro Shimoda
2023-08-25 9:32 ` [PATCH v20 16/19] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support Yoshihiro Shimoda
2023-09-14 16:34 ` Bjorn Helgaas
2023-09-15 9:37 ` Yoshihiro Shimoda
2023-09-15 20:38 ` Bjorn Helgaas
2023-09-19 7:03 ` Yoshihiro Shimoda
2023-09-14 16:58 ` Bjorn Helgaas
2023-09-15 9:37 ` Yoshihiro Shimoda
2023-08-25 9:32 ` [PATCH v20 17/19] PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
2023-08-25 9:32 ` [PATCH v20 18/19] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
2023-08-25 9:32 ` [PATCH v20 19/19] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller Yoshihiro Shimoda
2023-08-25 18:27 ` [PATCH v20 00/19] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Serge Semin
2023-08-27 6:59 ` Krzysztof Wilczyński
2023-08-28 1:19 ` Yoshihiro Shimoda
2023-08-28 6:37 ` manivannan.sadhasivam
2023-08-28 13:58 ` Serge Semin
2023-08-29 12:02 ` Yoshihiro Shimoda
2023-08-28 16:07 ` Krzysztof Wilczyński
2023-08-29 12:13 ` Yoshihiro Shimoda
2023-08-27 16:27 ` Krzysztof Wilczyński
2023-08-31 1:34 ` Yoshihiro Shimoda
2023-08-31 14:04 ` Krzysztof Wilczyński
2023-09-01 0:20 ` Yoshihiro Shimoda
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ZbgpzPjS7Jhe8fq5@lizhi-Precision-Tower-5810 \
--to=frank.li@nxp.com \
--cc=bhelgaas@google.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=fancer.lancer@gmail.com \
--cc=gustavo.pimentel@synopsys.com \
--cc=jingoohan1@gmail.com \
--cc=kishon@kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kw@linux.com \
--cc=linux-pci@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=marek.vasut+renesas@gmail.com \
--cc=robh+dt@kernel.org \
--cc=yoshihiro.shimoda.uh@renesas.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.