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From: "Roger Pau Monné" <roger.pau@citrix.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: xen-devel@lists.xenproject.org, Jan Beulich <jbeulich@suse.com>,
	Wei Liu <wl@xen.org>
Subject: Re: [PATCH 0/3] x86/intel: expose additional SPEC_CTRL MSR controls
Date: Tue, 30 Jan 2024 18:18:23 +0100	[thread overview]
Message-ID: <ZbkvX857u0lESr21@macbook> (raw)
In-Reply-To: <85794e25-03bd-47b8-90b4-c08fbbd5a756@citrix.com>

On Tue, Jan 30, 2024 at 04:25:40PM +0000, Andrew Cooper wrote:
> On 30/01/2024 9:13 am, Roger Pau Monne wrote:
> > Roger Pau Monne (3):
> >   x86/intel: expose IPRED_CTRL to guests
> >   x86/intel: expose RRSBA_CTRL to guests
> >   x86/intel: expose BHI_CTRL to guests
> 
> A couple of things.  First,
> 
> diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
> index a04a11858045..382bc07785d0 100644
> --- a/xen/arch/x86/msr.c
> +++ b/xen/arch/x86/msr.c
> @@ -309,8 +309,8 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr,
> uint64_t *val)
>  
>  /*
>   * Caller to confirm that MSR_SPEC_CTRL is available.  Intel and AMD have
> - * separate CPUID features for this functionality, but only set will be
> - * active.
> + * separate CPUID features for some of this functionality, but only one set
> + * will be active on a single host.
>   */
>  uint64_t msr_spec_ctrl_valid_bits(const struct cpu_policy *cp)
>  {
> 
> 
> There was a typo (missing the one in "but only one set"), but you're
> also adding bits now which are Intel-only and very likely to stay that way.

Oh, didn't realize the existing typo.

> IPRED_CTRL finally gives Intel CPUs a control with a similar security
> property to AMD IBRS;  i.e. I doubt AMD are going to gain support for
> these bits when they already guarantee that property and have done for
> years already.
> 
> 
> Next, I can't say that I particularly love that indentation.  This seems
> marginally less bad
> 
>     return (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP |
>             (ssbd       ? SPEC_CTRL_SSBD       : 0) |
>             (psfd       ? SPEC_CTRL_PSFD       : 0) |
>             (cp->feat.ipred_ctrl
>              ? (SPEC_CTRL_IPRED_DIS_U | SPEC_CTRL_IPRED_DIS_S) : 0) |
>             (cp->feat.rrsba_ctrl
>              ? (SPEC_CTRL_RRSBA_DIS_U | SPEC_CTRL_RRSBA_DIS_S) : 0) |
>             (cp->feat.bhi_ctrl ? SPEC_CTRL_BHI_DIS_S : 0) |
>             0);
> 
> insofar as at least it's fewer lines.  Given the length of these new
> constants, I can't think of anything better.

I prefer my indentation, but it adds an extra line which might not be
desirable.

Feel free to adjust on commit.

Regards, Roger.


      reply	other threads:[~2024-01-30 17:18 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-30  9:13 [PATCH 0/3] x86/intel: expose additional SPEC_CTRL MSR controls Roger Pau Monne
2024-01-30  9:13 ` [PATCH 1/3] x86/intel: expose IPRED_CTRL to guests Roger Pau Monne
2024-01-30 10:57   ` Jan Beulich
2024-01-30 12:06     ` Roger Pau Monné
2024-01-30 12:59       ` Jan Beulich
2024-01-30 14:35         ` Roger Pau Monné
2024-01-30 14:47           ` Jan Beulich
2024-01-30 15:01             ` Roger Pau Monné
2024-01-30 15:46         ` Andrew Cooper
2024-01-30  9:13 ` [PATCH 2/3] x86/intel: expose RRSBA_CTRL " Roger Pau Monne
2024-01-30  9:14 ` [PATCH 3/3] x86/intel: expose BHI_CTRL " Roger Pau Monne
2024-01-30 10:27 ` [PATCH] XTF: tests SPEC_CTRL added bits Roger Pau Monne
2024-01-30 10:42   ` Jan Beulich
2024-01-30 11:46     ` Roger Pau Monné
2024-01-30 12:55       ` Jan Beulich
2024-01-30 15:02         ` Roger Pau Monné
2024-01-30 15:04           ` Andrew Cooper
2024-01-30 16:25 ` [PATCH 0/3] x86/intel: expose additional SPEC_CTRL MSR controls Andrew Cooper
2024-01-30 17:18   ` Roger Pau Monné [this message]

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